JPH0119273Y2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to a still image recording and reproducing device, and in particular uses a general-purpose, inexpensive disk recorder mechanism that does not have a precise servo system like a floppy disk, but allows fluctuations in rotational phase. The object of the present invention is to provide a still image recording and reproducing device that can perform the following steps.

This type of still image recording and reproducing device uses a disk recorder equipped with a precise rotational phase control system, which not only increases the cost, but also requires the use of inexpensive and popular floppy disks. The drawback was that it was unusable. In order to improve these drawbacks, it may be possible to extend the time axis of the A-D converted video signal and write and reproduce it as a digital signal on a floppy disk, but this would be impractical due to the large recording capacity. lack.

The present invention has been devised in view of the various drawbacks of the conventional examples.

The details will be explained below with reference to drawings showing main circuit block diagrams of one embodiment.

This still image recording/playback device basically includes a scan converter SC that can be used for both recording and playback systems;
an FM modulation circuit FM that modulates the analog video signal time-base converted by the converter;
It consists of a floppy disk recorder FDD, an FM demodulation circuit DM for demodulating the reproduced FM signal, and a clock pulse recording/reproducing circuit CR.

The scan converter SC has a short period (3sc,
However, the video signal inputted through the clock pulse generation circuit CG which independently generates a clock pulse of the color subcarrier frequency (sc is the color subcarrier frequency) and a clock pulse of a long period (1/10sc), and the first recording/playback switch _S1 , an A-D conversion circuit AD that samples and then quantizes the short-period clock pulse as a sampling pulse; and a field memory that reads the A-D conversion output of the circuit using the short-period clock pulse.
The contents of the RAM constituting the field memory are sequentially read out using the long-period clock pulses from VM and the clock pulse generation circuit CG, and the read data is converted back into an analog signal (bandwidth 140 KHz) with the time axis extended (10 times). D-A conversion circuit
Consists of DA.

The FM modulation circuit FM includes a second recording/playback switch S ₂
A multi-vibrator type modulation circuit that performs FM modulation on the 140KHz time-axis expanded video signal applied via the .

The above-mentioned floppy disk recorder FDD may be of a general-purpose servoless type, and may be of a type that allows a wide range of phase fluctuation errors in the rotational phase control system.

Further, the FM demodulation circuit FM can be of a pulse counter type or a PLL type, and demodulates the reproduced FM output of the floppy disk recorder FDD, and when reproducing the demodulated signal, the first recording/reproducing switch S ₁
It is applied as a reproduction input to the A/D conversion circuit AD through.

The clock pulse recording/reproducing circuit CR includes a 1/2 frequency dividing circuit DV for frequency dividing the long-period clock pulse of the clock pulse generating circuit CG, and a 1/2 frequency dividing circuit DV for dividing the long-period clock pulse from the floppy disk recorder, respectively, before and after the pulse recording/reproducing circuit (not shown). It is equipped with a multiplier circuit MP that frequency-multiplies the reproduction clock pulse, and in this embodiment, as the output of the FM modulation circuit FM is recorded and reproduced, the 1/10sc long-period clock pulse is frequency-divided and recorded, and after the reproduction, the disc recorder The phase of the base oscillation circuit of the clock pulse generating circuit CG is controlled by frequency-doubling the reproduced clock pulse embodying the rotational phase error, and the phase of the output of the clock pulse generating circuit CG is reflected in the reproduced signal of the disk recorder during reproduction. Vary proportionally to jitter component.

During playback, unlike during recording, the A-D conversion circuit AD samples and quantizes the output of the FM demodulation circuit DM using a long-period clock pulse as a sampling pulse, and operates in two modes so that it can perform A-D conversion. The DA converter circuit DA must be configured to operate, and the DA converter circuit DA can read out the contents of the field memory VM using a short period clock pulse as a reading clock pulse, and convert the digital signal into an analog signal. It must be configured to operate in two modes. However, this is not the case when scan converters are provided independently in each of the recording and reproducing systems.

Next, the operation of the device of the present invention will be explained. During recording, the video signal applied to the input terminal IN is
It is applied as an analog input to the A/D converter circuit AD via the first recording/reproducing switch _S1 which is switched to the solid line position. The video signal is sampled and quantized by this circuit using a short-cycle clock pulse stabilized at 3sc, and the same short-cycle clock pulse is used as an address control signal in the form of a digital signal to be sequentially sent to the RAM constituting the field memory VM in real time. written in. Of course, the above field memory
In the case of configuring 250 320-bit line memories, a configuration can be adopted in which the frequency-divided output of the above clock pulse is used as a shift pulse for the shift register forming the line memory, and digitized video signals are sequentially written. Bye.

The contents of the field memory VM are immediately read out by a long period (1/10sc) clock pulse,
After being converted into a time-axis expanded video signal having a band of 140 KHz in the DA conversion circuit DA, it is applied as a modulation input to the FM modulation circuit FM via the second recording/reproduction switch _S2 . On the other hand, the long-period clock pulse of the clock pulse generation circuit CG mentioned above is generated by a frequency dividing circuit.
DV is converted to 179KHz, multiplexed into an FM modulated signal with a deviation of 200-240KHz, or added to the floppy disk recorder FDD by a separate magnetic head (not shown) for magnetic recording. .

During playback, the playback output of the floppy disk recorder FDD is demodulated by the FM demodulation circuit FM,
While the time axis expansion signal in the 140 KHz band is present, it is applied as an analog signal input to the A/D conversion circuit AD through the first recording/reproducing switch _S1 which is switched to the playback position. This analog signal is a long-period clock pulse 1/10sc (floppy clock pulse) which is the frequency-divided output of a clock pulse generation circuit CG, which can be configured with a PLL oscillation circuit whose reference input is the output of a multiplier circuit MP that multiplies the reproduced clock pulse. Since it embodies the jitter component of a disk recorder, it is expressed with a dash "'" (hereinafter the same) is sampled, and after being A-D converted as a clock pulse,
The outputs of the clock pulse generation circuit CG are sequentially written into the field memory VM. 1
When all the data equivalent to the field is written,
The contents are sequentially read out at high speed by the output 3s'c of the clock pulse generation circuit CG, and then D-A converted again and outputted as a reproduced video signal via the second recording/reproducing switch _S2 . Ru.

In addition, as another embodiment, the scan converter SC can be replaced with an analog memory such as a CDD element or a BBD element. In that case, the clock pulses for transferring storage charges are applied correspondingly, but the above-mentioned AD and DA conversion circuits are not required.

Since the present invention has the above-mentioned configuration, it is an inexpensive configuration that combines a disk recorder that does not require a precision rotational phase servo system like a general-purpose floppy disk recorder with a memory that does not require as much storage capacity. It is possible to realize a recording and reproducing device for high-quality still images without jitter.

[Brief explanation of the drawing]

The drawing is a block diagram of the main parts of the still image recording and reproducing apparatus of the present invention. SC...Scan converter, CG...Clock pulse generation circuit, FM...FM modulation circuit, FDD...
...Floppy disk recorder, DM...FM demodulation circuit.

Claims (1)

[Claims for Utility Model Registration] (1) At the time of recording, a means for converting a video signal to be recorded into a digital signal and writing it into a field memory using a short-period clock pulse of a clock pulse generating means; The video signal output of a scan converter and the long-period clock pulse are simultaneously read out at a low speed by the long-period clock pulse of the generating means and D/A conversion means for D/A conversion into a video signal whose time axis has been expanded again. A still image recording and reproducing apparatus configured to perform scan conversion again using the long-period clock pulse written on a floppy disk and reproduced during reproduction to return the time axis to the original and obtain a reproduced video signal. (2) The scan converter controls the clock pulse generation means with the reproduced long-period clock pulse, converts the reproduced analog signal from analog to digital, and writes it into the field memory using the long-period clock pulse of the clock pulse generation means. and means for sequentially reading out the contents of the field memory using short-period clock pulses from the clock pulse generating means and converting the contents from D to A. Still image recording and playback device.