JPH01190173A - Synchronizing circuit for optical scanner - Google Patents

Abstract

PURPOSE:To surely improve the synchronizing accuracy and inexpensively and to improve the picture quality by providing a delay clock management circuit preventing the selection of a clock signal except the selected picture scanning clock as the picture scanning clock. CONSTITUTION:A latch circuit 13 outputs latch signals Q1-Qn+1 by the rising of a signal DETP of an optical sensor 6. A delay clock management circuit 14 discriminates the level of the latch signal to be inputted and when the level of a signal, e.g., Qk is at L and the next signal Qk+1 is at H, then the output Sk corresponding to the latch signal Qk is brought into L and the other is brought into H. A clock selection circuit 15 receives signals S1-Sn and clock groups CK1-CKn and the clock CKk corresponding to the signal Sk whose level is at L in matching with the phase of the optical detection signal DETP optimizingly is selected and outputted to a picture control circuit 8 as the picture scanning clock WCLK. Thus, the synchronization accuracy is increased inexpensively and surely to improve the picture quality.

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a synchronization circuit for an optical scanning device, and in particular, to synchronize image writing in an optical scanning device that scans a laser beam using a rotating deflector used in a laser printer or the like. Regarding synchronous circuits for

A light beam is scanned over the object to be scanned using a rotary deflector, and image writing is synchronized by the output of a photosensor installed outside the image scanning area, so that the image is written on the photoreceptor, which is the object to be scanned. An optical scanning device configured to form a laser beam is used in, for example, a laser printer.

In this case, due to manufacturing errors in the rotating deflector, up to one pixel worth of jitter may occur in the main scanning direction, reducing image quality.
Conventionally, an original signal with a frequency n times that of the image scanning clock is applied to a 1/n frequency divider, and the frequency divider is reset when a light beam is detected, or the frequency is converted from the reference clock signal by a delay circuit. By creating a group of (n-1) clock signals whose phases are sequentially delayed and selecting the signal whose phase matches the output of the upper light distribution sensor as the image scanning clock, the jitter is reduced to about 1/n pixels. I kept it to a minimum.

However, when n is increased in order to obtain good image quality, the former requires a higher frequency of the original signal, making the circuit more sophisticated and complex, and the latter requires increasing the accuracy of the delay circuit to prevent malfunctions. Both methods had disadvantages such as increased costs.

■-F This invention was made in view of the above points, and aims to inexpensively and reliably increase the accuracy of synchronization without increasing the performance of elements or circuits, and to improve the image quality of images written by an optical scanning device. purpose.

(2) In order to achieve the above-mentioned object, the present invention scans an object with a light beam using a rotating deflector, and generates a reference clock signal and a group of clock signals having the same frequency and sequentially delayed phases as the reference clock signal. In the synchronization circuit of the optical scanning device, which synchronizes image writing by selecting one clock signal as the image scanning clock based on the output of the optical sensor provided outside the image scanning area, the clock signal other than the selected image scanning clock is used. A delay clock management circuit is provided for managing the clock signal such that the clock signal is not selected as the image scanning clock.

Hereinafter, the present invention will be specifically explained based on embodiments.

First, the optical system of the optical scanning device to which the present invention is applied will be explained with reference to FIG.
After being deflected by a rotating deflector 3 consisting of a rotating polygonal mirror, it is imaged as a scanning spot by an fθ lens 4 onto a photoreceptor 5, which is an object to be scanned.

This laser beam is modulated by a recording signal, and is main-scanned over the surface of the photoreceptor 5 by the rotary deflector 3 to form an electrostatic latent image thereon. Sub-scanning is performed by rotating the photoreceptor 5 around its axis.

The optical sensor 6 is a photodetecting element such as a photodiode provided outside the image scanning area on the main scanning line, and detects the laser beam from the rotating polarizer and outputs a photodetection signal DETP.

Next, the electrical control system of this optical scanning device will be explained with reference to FIG.

The synchronous circuit 7 is a circuit targeted by the present invention, and functions as an image scanning clock generation circuit, and when the optical detection signal DETP is input from the optical sensor 6, it outputs an image scanning clock WCLK synchronized therewith to the image control circuit 8. .

As mentioned above, since the optical sensor 6 was provided outside the image scanning area, the image control circuit 8 counted the image scanning clock WCLK until the light beam reached the image scanning area or a further predetermined space was taken. After that, a control signal is started to be sent to the character generator 9.

The character generator 9 outputs an image information signal synchronized with the image scanning clock WCLK for each main scanning line based on the control signal, which is transmitted to the optical drive circuit 1 via the image control circuit 8.
Sent to 0.

The light source drive circuit 10 modulates (blinks) the semiconductor laser 1 shown in FIG. 2 in accordance with the image information signal, and forms one line of electrostatic latent image on the photoreceptor 5.

Although an example in which a semiconductor laser is used as the light source has been described, it is also possible to use a gas laser, such as a He-Ne laser, as the light source, and use a light modulation element such as an acousto-optic element driven by the light source drive circuit 10 instead of the collimator lens 2. It may be arranged to modulate the laser beam.

FIG. 1 is a block circuit diagram showing an embodiment of a synchronization circuit 7 according to the present invention.

This synchronization circuit 7 includes a reference clock oscillator 11° delay circuit 12. Latch circuit 13. Delay clock management circuit 14. and a clock selection circuit 15.

The reference clock oscillator 11 generates an image scanning clock WCLK.
oscillates and outputs a reference clock signal (hereinafter "signal" will be omitted) CKI having a frequency equal to that of .

The delay circuit 12 inputs the reference clock CK1 and outputs from n output terminals a group of clock signals (hereinafter "signals" will be omitted) that have the same frequency and waveform as the reference clock CKl and whose phase is delayed by approximately 1/n of the period. ) CN3. CN3.
...Outputs CKn+1.

The latch circuit 13 receives a light detection signal DET from the light sensor 6.
When P rises, (n+1) inputs are latched and latch signals Q1 to Qn+1 are output.

The delay clock management circuit 14 receives the input latch signal Q1.
~Qn+1 level is determined, for example, latch Fo No.Q
Select the latch signal where the level of k (k = 1 to n) is °L" and the level of the next latch signal Qk+t is °H" (if there are two or more, k is the smallest) Then, the output Sk corresponding to the latch signal Qk is °L°,
It outputs n outputs 81 to Sn with the others set to H''.

The clock selection circuit 15 inputs the n signals 81 to Sn and the n clock groups CKI to CK, and selects, for example, the optical detection signal DE from among the clock groups GKI to CKn.
The clock that has the most phase with TP, that is, the level is °
The clock CKk corresponding to the signal Sk at L° is selected and outputted to the image forming circuit 8 as the image scanning clock WCLK.

FIG. 4 is a circuit diagram showing an example of the latch circuit 13 and delay clock circuit 14 that constitute the synchronization circuit 7 shown in FIG. 1, and FIG. 5 is a circuit diagram showing an example of the clock selection circuit 15. It is.

FIG. 6 shows that in FIG. 1, FIG. 4, and FIG. 5, n=
6 is a timing chart for explaining an example of operation in the case of 6.

As shown in FIG. 4, the latch circuit 13 includes (n+1) up-edge type D-FF (D flip-flop) circuits F.
It is composed of FI to FFn+1, and each CP terminal is commonly connected to receive the light detection signal DETP from the light sensor 6. Clocks CKI to CKn+t are input to each terminal of these D-FF circuits FF1 to FFn+1, respectively, and latch signals Q1 to Qn+ are input from each Q terminal, respectively.
1 is output.

When the optical sensor 6 detects a laser beam, as shown in FIG. 6, the clock CKI - CKn+1 (CK7 in this example) is latched by the rising edge (a) of the optical detection signal DETP, and the clock is latched according to the level of each clock at that time. Therefore, the latch signals Q1 to Qn+x (Q?) are held at H° or L′ regardless of their previous levels.

The delay clock management circuit 14, as shown in FIG.
n management circuits 201 to 20n from the first stage (top stage) to the nth stage (bottom stage) and mutually adjacent management circuits from the first stage to the n-1 stage are coupled (n- 2) inverters 211 to 21n-z.

The first stage (top stage) management circuit 201 includes a knot circuit 22
Each management circuit 20 from the second stage to the n-1th stage is composed of an AND circuit 23, a NOR circuit 24, and a NAND circuit 25.
2-2On-x also has exactly the same configuration.

The n-th stage (lowest stage) management circuit 20n includes a NOT circuit 22, an AND circuit 23, and a NAND circuit 25.

Each AND circuit 25 in the management circuit 20 of the first stage (intermediate stage, 2 to n-1) receives the latch signal Qk input from the terminal Ik and inverted by the NOT circuit 22, and the terminal Ik÷1 A latch signal Qk+x inputted from is inputted, and an AND operation is performed between the two.

The outputs Qk+x and Qk of the AND circuit 23 are input to input terminals of a NOR circuit 24 and a NAND circuit 25, respectively.

The other input terminals of each NOR circuit 24 in the management circuit 20 include
The output of the NOR circuit 24 of -1 is inputted to the adjacent front-stage management circuit 20 via -1 to the inverter 21, and the output of the AND circuit 23 is NORed with Qk+1.Qk, and the results are the adjacent ones. It is output to the management circuit 20 at the next stage as +1.

The output of the NOR circuit 24 at the previous stage is input as is to the other input terminal of each NAND circuit 25 in the management circuit 20, and the output of the AND circuit 23 is NANDed with the output Qk+x·Qk of the AND circuit 23, and the result is is the delay clock management circuit 14
is output as the output signal Sk.

The nth stage (final stage) management circuit 20n is similar to the intermediate stage management circuit 20 described above, except that the NOR circuit 24 that outputs to the next stage management circuit is omitted.

The first-stage management circuit 201 is almost the same as the intermediate-stage management circuit, but one input terminal of the NOR circuit 24 is grounded (
'L'), and one input terminal of the NAND circuit 25 is connected to the power supply line ('H-).

Therefore, the NOR circuit 24 and the NAND circuit 25 act as a NOT circuit, and both output Ql and Ql.

Therefore, the output Sk of the NAND circuit 25 and the output Sk' of the NOR circuit 24 to the management circuit 20 of each stage of k=1 to n can be expressed by the following logical formula.

k=1:51=S1:Ql・Ql=3:53=
Q4・dan・S2′ =Q4 stone・(Q3・2+Q2・−possible) S3′:Q4・
Q3+5z =Q4・Q3+Q3・possible+Q2・Qz Similarly, when k≧2, 5k=Qk+1・i・=(Qk−teV clove Qk−1・te=T”i+・・・・・・+Q3・■+Q2・Tere）Here, Pk=Qk+1・Qk S I Gk=Qk−Kaichi+Qk−1・Kou Y Takumi+...
・・・+Q2・酊一1=、ΣPi 1工l However, if 5IG1=O, then 5k=Pk-5IGk=Pk+S IGk.

For example, as shown in FIG. 6, when n=6, the output S1 of the delayed clock management circuit 14 when the clocks GK1 to CK7 are latched by the rising edge (a) of the photodetection signal DEPT from the optical sensor 6 The logical values of ~S6 are as shown in Table 1 from the above relational expression.

Table 1 also shows that, for example, the rise of the photodetection signal DEPT is (b), (
If it were in the position c), the outputs S1 to S6 of the delayed clock management circuit 14 would be as shown in Tables 2 and 3, respectively.

Table 2 Table 3 As is clear from the logical values shown in Tables 1 to 3, (
In the case of a), (b), and (c), the delay clock management circuit 1
Only S2, ts3ys5, and 4 outputs are "L-", and the other outputs are H°.

A combination in which the level of the latch signal Qk is L° and the level of the next latch signal Qk+x is H° is, for example, the case (a) shown in Table 1.

There are two latch signals with k=2.6, but only the output S2 corresponding to the latch signal Q2 with a small k is at L°.

As a result, n outputs 81 to Sn are obtained in which only the output Sk corresponding to the latch signal Qk of the clock CKk with the smallest jitter with respect to the rise of the photodetection signal DETP is set to °L, and the others are set to H°. .

Further, in the example shown in FIG. 6, the clock Ck6.

The phase of Ck7 lags the phase of the reference clock Ckx by one cycle or more. This is because the delay time of the delay circuit 12 is set to be slightly larger than l/n of the period of the reference clock Ckl so that there is no problem even if the delay time of the delay circuit 12 changes due to the ambient temperature or other causes.

Since the delayed clock management circuit 14 shown in this embodiment operates as described above, the output corresponding to the clock delayed by one period or more will not become L° by mistake.

For example, as shown in FIG.
negative logic AND circuits (practical NOR circuits) 301~
30n and one NOR circuit 31 having n inputs.

In the n negative logic AND circuits 3Qk (k=1 to n),
Each corresponding output Sk of the delayed clock management circuit 14
and the clock CKk output from the reference clock oscillator 11 and the delay circuit 12 are input, and all of their outputs are input to the NOR circuit 31.

In the state (a) shown in FIG. 6 (Table 1), only Sl is at L and the other Sls and S3 to Sn are at H, so the AND circuits 501, 303 to 30n in FIG. The output is L°, and only the AND circuit 302 outputs CK2. Therefore,
The output CK2 of the NOR circuit 31 becomes the output of the clock selection circuit 15, that is, the selected image scanning clock WC:LK output from the synchronization circuit 7.

Similarly, in the state (b) or (c) (Table 2 or 3), only S3 or S5 is at °L°, so the clock C is used as the image scanning clock WCLK.
K3 or CKs is output.

Generally, a slight timing delay may occur while the clocks CKx to CKn pass through the latch circuit 14 and the delayed clock management circuit 15 and are converted to the outputs 81 to Sn. Therefore, the signals 81 to 81 to be input to the clock selection circuit 15
Sn will deviate from the directly inputted clocks CKI to CKn.

In such a case, as shown in FIG. 7, in the clock selection circuit 15 shown in FIG. The combination may be shifted according to the timing delay.

For example, when the timing delay of the signal S is more than one time and less than twice the unit delay time of the delay circuit 12, the combined clock GK is shifted by two, and as shown in the figure, the negative logic AND circuit 30k is supplied with the signal Sk. and clock cKk+2 are input in combination.

If (k+2))n, the clock CKk+2−
Enter n. That is, AND circuit 30n-z *
30n-1 and 5On each have a signal 5n-z l
5n-1) Sn and clocks CKn, CKt
5CK2 may be input.

In this way, even if the combinations of the signals S1 to Sn output from the delayed clock management circuit 14 and the clocks CK1 to CKn are shifted, the effect of suppressing jitter to a small level does not change.

As explained above, according to the present invention, even if the delay time of the delay circuit changes due to changes in ambient temperature, etc., a clock other than the predetermined clock will not be mistakenly selected, and the delay time will be reduced by 1/n minutes. Since it does not handle high frequencies like the circuit circuit method, there is no need to increase the accuracy of the entire circuit, and adjustment is easy, and the image scanning clock WCLK is always optimal.
can be output accurately.

An example has been described above in which the laser printer uses the semiconductor laser 1 as the light source and performs optical scanning using a rotating deflector such as a polygon mirror. Alternatively, the present invention can be similarly applied to an optical scanning device that uses a rotating mirror or the like, which rotates the mirror around its axis by a servo drive system using a rotating magnetic field, as a rotating deflector.

As explained above, the synchronization circuit for an optical scanning device according to the present invention inexpensively and reliably increases the precision of synchronization without increasing the performance of elements or circuits, and improves the image quality of images written by the optical scanning device. can be done.

[Brief Description of the Drawings] Fig. 1 is a block circuit diagram of a synchronous circuit according to an embodiment of the present invention, Fig. 2 is a block diagram showing an example of the optical system of the optical scanning device, and Fig. 3 is a block diagram of the same. A block diagram of the electrical control system, Figure 4 shows the latch circuit 13 and delay clock circuit 14 in Figure 1.
Circuit diagram showing an example. FIG. 5 is a circuit diagram showing an example of the clock selection circuit 15 in FIG. FIG. 6 is a timing chart for explaining the operation of this embodiment, and FIG. 7 is a circuit diagram showing another example of the clock selection circuit 15 in FIG. 1. 1... Semiconductor laser 2... Collimator lens 3
... Rotating deflector 4 ... fθ lens 5 ... Photoreceptor 6 ... Optical sensor 7 ... Synchronous circuit ・
8... Image control circuit 11... Reference clock oscillator 12... Delay circuit 13... Latch circuit 14...
...Delayed clock management circuit 15...-Clock selection circuit 20...Management circuit 21...Inverter 22...
...NOR circuit 23...AND circuit 24...NOR circuit 25...NAND circuit 30...Negative logic AND circuit 31...n-input NOR circuit Figure 2, Figure 3, Figure 5, l Fig. 7, No. Kozue Mound 1,
~ Watching Hani Biting Yaaaaa
t/ltl'lt/) ψ VrVrg≧

Claims (1)

[Claims] 1 A light beam is scanned over the scanning object by a rotating deflector, and an optical sensor installed outside the image scanning area is selected from among a reference clock signal and a group of clock signals whose frequency is equal to that of the reference clock signal and whose phase is sequentially delayed. In a synchronization circuit of an optical scanning device that synchronizes image writing by selecting one clock signal as an image scanning clock based on the output of the image scanning clock, a clock signal other than the selected image scanning clock is not selected as the image scanning clock. A synchronous circuit for an optical scanning device, characterized in that a delay clock management circuit is provided to manage the delay clock.