JPH06189082A - Phase selector - Google Patents

Abstract

PURPOSE:To latch a horizontal synchronizing signal to a divided picture element clock always at optimum timing without shifting it, to exclude operational delay caused by temperature dependency and to provide high-definition images. CONSTITUTION:This device is provided with a VCO 305 for outputting plural signals such as reference clocks, phase selection circuit 307 for selecting one phase signal from inverted/non-inverted outputs after respective output signals are latched, adder circuit 308 for shifting the selected phase signal and outputting it as a phase signal for phase comparison, D flip-flop 310 for storing the phase signal at the change point of the horizontal synchronizing signal, and phase comparator 303 for comparing the phase signal, which is synchronized with the edge of the horizontal synchronizing signal synchronizing an output edge at the specified step of the VCO 305, with the reference clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase selection device using a PLL circuit used in a writing system of a laser printer, a digital copying machine, a laser facsimile, etc., and more particularly to a voltage control type ring oscillator. The present invention relates to a phase selection device for stabilizing the operation by performing phase selection so that an output edge of a specific stage is synchronized with an edge of a horizontal synchronization signal synchronized with a reference clock.

[0002]

2. Description of the Related Art In a raster scanning type printer such as a laser printer, multi-gradation writing is executed in response to a demand for higher image quality. In this multi-gradation writing, one pixel is divided into several parts for printing. At that time, a pixel clock (reference clock signal WCLK1) indicating one pixel is used as a PLL (Phase-lock) using a reference clock signal VCO.
The divided clock signals (+ T1 to -T) having the same frequency as the pixel clock but different phases are generated using the ed loop) circuit.
4) is oscillating.

On the other hand, the optical detection signal DETP from the optical sensor
Since the horizontal synchronization signal LSYNC1 generated based on the reference clock operates in synchronization with the pixel clock (reference clock signal WCLK1), the divided clock signal obtained by locking the horizontal synchronization signal LSYNC1 with the reference clock signal in the PLL with a phase error. Must be synchronized again (+ T1 synchronization in the present invention). Therefore, one of the phases of the divided clock is taken out and the horizontal synchronizing signal LSYNC1 is latched.

Further, as reference technical documents relating to the present invention, "synchronization circuit of optical scanning device" disclosed in Japanese Patent Laid-Open No. 63-243910, Japanese Patent Laid-Open No. 60-208245.
There is a "driving device for a recording device" disclosed in Japanese Patent Laid-Open Publication No. 2003-242242, which shows a synchronization means for a reference clock signal WCLK1.

[0005]

However, in the conventional technique as described above, since the VCO and the phase comparator are composed of semiconductors, they have temperature dependence, and the phase of the PLL changes depending on the temperature change. Since the error is not constant and the writing system circuit uses a high-speed clock, the phases of the reference clock and the divided clock signal used for passing the horizontal synchronization signal LSYNC1 must be controlled so that the phases will shift due to the passage of time, and setup or hold will occur. There is a problem in that the quality of the image is deteriorated due to the inability to secure the time.

The present invention has been made in view of the above, and makes it possible to latch the divided pixel clocks without shifting the horizontal synchronizing signal at the optimum timing at all times, thereby eliminating the operation delay due to the temperature dependence. ， The purpose is to obtain high-quality images.

[0007]

In order to achieve the above object, the present invention provides a reference clock and an oscillating means for outputting a plurality of signals having the same frequency and different phase as the reference clock, and each of the oscillating means. After latching the output signal, a phase selecting means for selecting one phase signal from the inverted / non-inverted output, and a shift for shifting the phase signal selected by the phase selecting means and outputting it as a phase signal for phase comparison Means, a phase storage means for storing the phase signal output from the shift means at a change point of the horizontal synchronizing signal, and an output edge at a specific stage of the oscillating means for synchronizing with an edge of the horizontal synchronizing signal synchronized with a reference clock. Phase comparison means for comparing the phase signal with the reference clock, and a horizontal synchronization signal for synchronizing the output edge of the specific stage of the oscillation means with the reference clock. Tsu is to provide a phase selector for phase selection to synchronize the di.

Further, it is preferable that the shift means shifts the selected phase signal by a preset number of stages.

Further, a reference clock and an oscillating means for outputting a plurality of signals having the same frequency as the reference clock but different phases, and after latching each output signal of the oscillating means,
From the shift means, a phase selection means for selecting one phase signal from the inverted / non-inverted outputs, a shift means for shifting the phase signal selected by the phase selection means and outputting it as a phase signal for phase comparison, Phase storage means for storing the output phase signal at a change point of the horizontal synchronizing signal, and a phase signal and a reference clock in which an output edge at a specific stage of the oscillating means is synchronized with the edge of the horizontal synchronizing signal synchronized with the reference clock. The present invention provides a phase selection device which is provided with a phase comparison means for comparing with each other and does not execute the phase selection during the image writing period.

Further, a reference clock and an oscillating means for outputting a plurality of signals having the same frequency as the reference clock but different phases, and after latching each output signal of the oscillating means,
From the shift means, a phase selection means for selecting one phase signal from the inverted / non-inverted outputs, a shift means for shifting the phase signal selected by the phase selection means and outputting it as a phase signal for phase comparison, Phase storage means for storing the output phase signal at a change point of the horizontal synchronizing signal, and a phase signal and a reference clock in which an output edge at a specific stage of the oscillating means is synchronized with the edge of the horizontal synchronizing signal synchronized with the reference clock. The present invention provides a phase selection device which comprises a phase comparison means for comparing, and performs phase selection when the horizontal synchronizing signal is active, and stores the selected or shifted phase signal when inactive.

Further, a reference clock and an oscillating means for outputting a plurality of signals having the same frequency as the reference clock but different phases, and after latching each output signal of the oscillating means,
From the shift means, a phase selection means for selecting one phase signal from the inverted / non-inverted outputs, a shift means for shifting the phase signal selected by the phase selection means and outputting it as a phase signal for phase comparison, Phase storage means for storing the output phase signal at a change point of the horizontal synchronizing signal, and a phase signal and a reference clock in which an output edge at a specific stage of the oscillating means is synchronized with the edge of the horizontal synchronizing signal synchronized with the reference clock. The present invention provides a phase selection device that includes a phase comparison unit that compares the phase selection means that does not update the stored phase signal for phase comparison during the image writing period.

Further, a reference clock and an oscillating means for outputting a plurality of signals having the same frequency as the reference clock but different phases, and after latching each output signal of the oscillating means,
From the shift means, a phase selection means for selecting one phase signal from the inverted / non-inverted outputs, a shift means for shifting the phase signal selected by the phase selection means and outputting it as a phase signal for phase comparison, Phase storage means for storing the output phase signal at a change point of the horizontal synchronizing signal, and a phase signal and a reference clock in which an output edge at a specific stage of the oscillating means is synchronized with the edge of the horizontal synchronizing signal synchronized with the reference clock. The present invention provides a phase selection device that includes a phase comparison unit that compares the phase signals, and does not update the phase signal for phase comparison when no phase signal is selected.

[0013]

In the phase selecting apparatus according to the present invention, the reference clock as a pixel clock and the phase signal (divided clock) used for the horizontal synchronizing signal are always equal in phase except during the image writing period, and the horizontal synchronizing signal is kept constant. It is latched to the divided pixel clock without shifting, and stable operation is obtained by eliminating temperature dependence when using a high-speed clock.

During the image writing period, the phase difference between the divided clocks output by the oscillating means is not constant. Therefore, the reference clock and the divided clocks are fixed to secure the writing position in each main scanning line. ， Get high quality images.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is an explanatory diagram showing a schematic configuration of a laser scanning device to which the present invention is applied. In the figure, 101
Is a semiconductor laser that modulates and outputs a laser beam, 102 is a collimator lens that shapes the laser beam incident from the semiconductor laser 101 into parallel light, and 103 is a rotating polygonal surface that has a mirror surface on the side of a regular polygon and rotates at high speed. mirror,
Reference numeral 104 denotes an fθ lens for optically converting and correcting a laser beam having an equiangular pitch deflected and scanned by the rotary polygon mirror 103 into an equal linear pitch, and 105 denotes a photosensitive drum that forms an electrostatic latent image based on an electrophotographic process, Reference numeral 106 denotes an optical sensor including a photodetector element such as a photodiode provided outside the image recording area on the main scanning line.

The operation of the laser scanning device configured as described above will be described. The laser beam emitted from the semiconductor laser 101 is shaped into parallel light by the collimator lens 102. The parallel light is incident on the rotating polygon mirror 103 rotating at a high speed, deflected and scanned by the rotation, converted into an equal linear pitch by the fθ lens 104, corrected, and then irradiated on the surface of the photosensitive drum 105. This laser beam is modulated in accordance with the recording signal, and the rotary polygon mirror 103 scans the surface of the photosensitive drum 105 to form an electrostatic latent image. Further, the photosensitive drum 105 is driven to rotate about its axis to perform sub-scanning. Further, since the optical sensor 106 is outside the image recording area on the main scanning line, it detects the laser beam on the main scanning line by the rotary polygon mirror 103 and outputs a light detection signal DETP.

FIG. 2 is an explanatory diagram showing a schematic configuration of a control system in the laser scanning device shown in FIG. In the figure, 201 is a light detection signal DET from the light sensor 106.
A synchronizing circuit 202 receives P and outputs a reference clock signal WCLK1 and a horizontal synchronizing signal LSYNC1, 202 is a PL
A divided clock generation circuit which uses the L circuit and which receives the reference clock signal WCLK1, the horizontal synchronization signal LSYNC1, and the image area signal FGATE and outputs a divided clock signal, 203 is a divided clock signal output from the divided clock generation circuit 202 A character generator that outputs an image information signal based on the following: 204 is an image control circuit that executes various controls related to image formation; 205 is a light source drive circuit that modulates the semiconductor laser 101 based on the output signal of the image control circuit 204. is there.

The operation of the above configuration will be described. The synchronization circuit 201 functions as a reference clock generation circuit, and when the photodetection signal DETP from the photosensor 106 is input, it outputs the reference clock signal WCLK1 synchronized with the photodetection signal DETP to the divided clock generation circuit 202. Further, since the optical sensor 106 is installed outside the image recording area, the synchronizing circuit 201 outputs the horizontal synchronizing signal LSYNC1 to the divided clock generating circuit 202 when the laser beam reaches the image recording area.

Next, the divided clock generation circuit 202 generates a divided clock signal for the reference clock signal WCLK1 by using a PLL circuit and further latches it by using the divided clock signal to generate a second horizontal synchronizing signal LSYNC2 and LSYNC2. WCLK2, which is one of the divided clock signals, is output to the character generator 203. The character generator 203 generates a divided clock signal WC for each main scanning line based on this control signal.
An image information signal synchronized with LK2 is output, and the image information signal is output to the light source driving device 205 via the image control circuit 204. The light source driving device 205 modulates and controls the semiconductor laser 101 on the basis of the input image information signal.
As shown in FIG. 5, an electrostatic latent image for one line of main scanning is formed on the surface of the photosensitive drum 105 by optical scanning.

FIG. 3 is a block diagram showing the configuration of the divided clock generating circuit shown in FIG. The oscillator 301 and the frequency divider 302 in the figure constitute the synchronizing circuit 201. In FIG. 3, reference numeral 303 is a circuit configured to output the phase difference between two clocks, which is configured by an RS latch,
3-state output phase comparator, 304 low-pass filter (hereinafter referred to as LPF), 305 voltage controlled ring oscillator (hereinafter referred to as VCO), 306 VCO3
Latch circuit for latching a plurality of outputs from 05, 307 is a phase selection circuit for selecting a phase, 308 is an addition circuit for performing a predetermined addition process, 309 is a multiplexer, 310 is three sets of D-type flip-flops ( D-FF
× 3), 311 are multiplexers.

Next, the operation of the divided clock generating circuit configured as described above will be described. Phase comparator 303
Is the reference clock signal WCLK1 from the frequency divider 302 and the clock signal WCLK from the multiplexer 311.
The phase difference of 2 is output, and the output digital signal is L
After being converted into an analog signal by being input to the PF 304, it is input to the VCO 305. The VCO 305 is an oscillator in which the frequency of oscillation is variable according to the input voltage, and is configured to output eight types of signals having the same frequency but different phases. The output from the VCO 305 is latched by eight kinds of outputs of the VCO 305 when the horizontal synchronizing signal LSYNC1 falls by the latch circuit 306 and becomes the active state.

The phase selection circuit 307 includes a latch circuit 306.
The change point of the VCO 305 output latched by is detected, and one of the VCO 305 outputs is selected and encoded into three digital signals (S0 to S2). The encoded signal is added to the shift amount of the selected phase designated by the three switches (SW) 308a by the adder circuit 308 composed of three sets of full adders, and the code of the divided clock signal for phase comparison is added. It is output as (A0-A2).

The code (A0 to A2) of the divided clock signal for phase comparison is output to three sets of D-type flip-flops 310 via the multiplexer 309 and stored at the rising edge of the second horizontal synchronizing signal LSYNC2. The stored code (Q0 to Q2) of the divided clock signal is input to the multiplexer 311, and the output 8 of the VCO 305 is output.
One of the books is selected and input to the phase comparator 303. As a result, a feedback loop is formed by the PLL, and the divided clock signal and the second horizontal synchronizing signal LSYNC2 synchronized with the divided clock signal are obtained.

As described above, the horizontal synchronization signal LSYNC1 is input according to the timing of inputting the horizontal synchronization signal LSYNC1.
By changing the clock for latching 1, the latch is always executed at the optimum timing, and it becomes possible to cope with the operation delay of the semiconductor due to the temperature change and the like when the high speed clock is used, so that stable operation is secured.

In the above, shifting the selected phase by the preset number of stages is performed by shifting the phase selection position with respect to the delay amount peculiar to the semiconductor used, and further, at the optimum position. This is to enable latching of the horizontal synchronization signal LSYNC1. Further, when the phase selection result is stored, it is executed after the horizontal synchronizing signal LSYNC1 becomes inactive, so that a sufficient margin is taken for the delay amount of the logic circuit and stable operation is secured.

By the way, in the above-described phase selection operation, the divided clocks for phase comparison are shifted with respect to the reference clock. In this case, however, there is a slight difference in the amount of phase difference between the divided clocks, so the image writing period If the above operation is executed during this, the slight amount of phase shift may be reflected at the time of writing, and fluctuation may occur on the image. Therefore, in the present invention, since the image writing period ends in a short time, the phase selection operation described above is executed during a period other than the image writing period and is stopped during the writing period to stabilize the image. Try.

That is, during the image writing period, the image area signal FGATE in the sub-scanning direction becomes Low level, the input of the horizontal synchronizing signal LSYNC1 to the latch circuit 306 is prohibited, and the phase selection operation is prohibited. The output of the multiplexer 309 is switched to the stored code (Q0 to Q2) of the divided clock signal so that the contents of the D-type flip-flop 310 are not rewritten. As a result,
Since a slight amount of deviation in the phase of each divided clock is not reflected in the image, vertical lines do not fluctuate, and a high-quality image can be obtained.

FIG. 4 is a timing chart showing each signal timing according to the present invention. In the figure, after the reference clock signal WCLK1 synchronized by the optical detection signal DETP output from the optical sensor 106 is input to the divided clock generation circuit 202 and is counted by the counter (not shown) to the image effective area, The horizontal synchronizing signal LSYNC1 is input. Divided clock generation circuit 2
02, the divided clock signal WCLK used for phase comparison
2 is selected by the phase selection operation, and phase comparison is executed.

FIG. 5 is a block diagram showing a schematic configuration of the phase selection circuit shown in FIG. In the figure, 501 is a priority encoder, 502 is an inverter, 503.
Is an AND gate. In the figure, + T is non-inverted output, -T
Indicates the inverted output of + T. Each output (+ T1 to -T4) line from the VCO 305 is connected to the AND gate 5
It is inverted and non-inverted to 03, and is connected at two places for each input having adjacent phases.

The operation of the above configuration will be described. As for the selected phase, a certain divided clock signal is Low
If the following phase at the level becomes High level, A
The ND gate 503 outputs High, and the selection of the phase is input to the priority encoder 501 to be encoded. In addition, other AND in which the phase was not selected
The gate 503 outputs Low. Further, when all the AND gates 503 are Low, it indicates that there is no selection result, and in this case, the signal EN for not rewriting the stored contents of the D-type flip-flop 310 is output.

As described above, when no phase is selected, the phase for phase comparison is not updated. This is a case in which the edge of the horizontal synchronizing signal LSYNC1 and the edge of each divided clock change almost at the same time, and no phase selection result may be obtained. In this case, an incorrect phase may be stored. When the wrong phase selection is performed on the line immediately before the image writing, it is executed to prevent the normal horizontal synchronization signal LSYNC1 from being latched during the image writing period.

FIG. 6 is a timing chart showing the process of phase selection according to the present invention. In this example, after the output + T1 from the VCO 305 is selected by the phase selection circuit 307, 1 is added by the adder circuit 308 and + T2. The case where the output is used for phase comparison is described. This will be described in detail. First, the reference clock signal WCLK
1 and a horizontal synchronizing signal LSYNC1 synchronized with the reference clock signal WCLK1 are input, and eight kinds of divided clock signals having the same frequency but different phases with respect to the reference clock signal WCLK1 are oscillated. Horizontal sync signal LSY
When NC1 falls (point a), the latch circuit 30
6 operates to generate 8 types of divided clock signals + T1 to -T4
Are latched and L0 to L7 are output. That is, [L0, L1, L2, L3, L4, L5, L6, L7]
= [0,1,1,1,1,1,0,0,0] is output. Adjacent phases are [0, 1]
, And as a result, + T1 is selected and + T
The code signal "0" of 1 is output to S0 to S2. Further, the shift amount "1" set by the switch (SW) 308a is added by the adder circuit 308, and "1" is output to A0 to A2 by "0 + 1->1" to the multiplexer 309.

Since the output of the adder circuit 308 is output to the output of the multiplexer 309 except when the image is being written, the D-type flip-flop 310 is LSYNC.
At the rising edge of 2, the contents of A0 to A2 change to Q0 to Q2, instructing the multiplexer 311 to use the divided clock signal + T2 for phase comparison, and outputting + T2 as WCLK2.

The effects of the above embodiments will be summarized and described below. Firstly, the clock for latching the horizontal synchronizing signal LSYNC1 is changed according to the timing of inputting the horizontal synchronizing signal LSYNC1, so that the clock can be always latched at the optimum timing, and the temperature change when the high-speed clock is used. Stable operation can be ensured in response to the semiconductor operation delay caused by the above. Second, it is possible to shift the phase selection position by the amount of delay peculiar to the semiconductor used, and it becomes possible to latch the horizontal synchronization signal LSYNC1 at the optimum position. Thirdly, since the phase selection is not executed during the image writing period, a slight shift amount of the phase of each divided clock is not reflected in the image, vertical line is not fluctuated, and a high quality image can be obtained. it can.

Fourth, by executing the horizontal synchronizing signal LSYNC1 after the inactive state, a sufficient margin can be taken for the delay amount of the logic circuit, and the clock used for phase comparison can be changed in a stable operation. It becomes possible. Fifth, since the stored phase for phase comparison is not updated during the image writing period, a slight deviation of the phase of each divided clock is not reflected in the image and vertical lines do not fluctuate. ， High quality image can be obtained. Sixth, even if no phase selection result is obtained, the correct phase comparison signal is not stored and the correct horizontal comparison signal LSYNC1 can be latched reliably.

[0036]

As described above, the phase selecting apparatus according to the present invention outputs the reference clock and the oscillating means for outputting a plurality of signals having the same frequency and different phase as the reference clock and the output signals of the oscillating means. After latching, reverse /
Phase selecting means for selecting one of the non-inverted outputs, shift means for shifting the phase signal selected by the phase selecting means and outputting it as a phase signal for phase comparison, and output from the shifting means. A phase storage means for storing a phase signal for changing the horizontal synchronizing signal at a change point of the horizontal synchronizing signal, and a phase signal for synchronizing an output edge at a specific stage of the oscillating means with an edge of a horizontal synchronizing signal synchronized with the reference clock and the reference clock. And a phase comparison means for performing phase selection so as to synchronize the output edge of the specific stage of the oscillation means with the edge of the horizontal synchronization signal synchronized with the reference clock, so that the horizontal synchronization signal is always shifted at the optimum timing. It can be latched to the divided pixel clock without needing to eliminate the operation delay due to temperature dependence and obtain a high-quality image.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a schematic configuration of a laser scanning device to which the present invention is applied.

FIG. 2 is a block diagram showing a schematic configuration of a control system of a laser scanning device to which the present invention is applied.

FIG. 3 is a block diagram showing a schematic configuration of a divided clock generation circuit according to the present invention.

FIG. 4 is a timing chart showing the timing of each signal according to the present invention.

FIG. 5 is a block diagram showing a schematic configuration of a phase selection circuit according to the present invention.

FIG. 6 is a timing chart showing a phase selection process according to the present invention.

[Explanation of symbols]

 201 Synchronous Circuit 202 Divided Clock Generation Circuit 303 Phase Selection Circuit 304 Low Pass Filter (LPS) 305 VCO (Voltage Controlled Ring Oscillator) 306 Latch Circuit 307 Phase Selection Circuit 308 Adder Circuit 310 D-Type Flip-Flop (D-FF × 3) 501 Priority encoder

Claims (6)

[Claims] 1. A reference clock and an oscillating means for outputting a plurality of signals having the same frequency and different phase as the reference clock, and one phase of an inverted / non-inverted output after latching each output signal of the oscillating means. Phase selecting means for selecting a signal, shift means for shifting the phase signal selected by the phase selecting means and outputting it as a phase signal for phase comparison, and a phase signal output from the shifting means for the horizontal synchronizing signal. Phase change means for storing at a change point and phase comparison means for comparing a reference clock with a phase signal in which an output edge at a specific stage of the oscillation means is synchronized with an edge of a horizontal synchronizing signal synchronized with a reference clock The phase is selected so that the output edge of the specific stage of the oscillating means is synchronized with the edge of the horizontal synchronizing signal synchronized with the reference clock. Phase selection device. 2. The phase selection device according to claim 1, wherein the shift means shifts the selected phase signal by a preset number of stages. 3. A reference clock and oscillating means for outputting a plurality of signals having the same frequency and different phase as the reference clock, and one phase of inverted / non-inverted output after latching each output signal of the oscillating means. Phase selecting means for selecting a signal, shift means for shifting the phase signal selected by the phase selecting means and outputting it as a phase signal for phase comparison, and a phase signal output from the shifting means for the horizontal synchronizing signal. Phase change means for storing at a change point and phase comparison means for comparing a reference clock with a phase signal in which an output edge at a specific stage of the oscillation means is synchronized with an edge of a horizontal synchronizing signal synchronized with a reference clock , A phase selection device characterized in that phase selection is not executed during the image writing period. 4. A reference clock and an oscillating means for outputting a plurality of signals having the same frequency and different phase as the reference clock, and one phase of inverted / non-inverted output after latching each output signal of the oscillating means. Phase selecting means for selecting a signal, shift means for shifting the phase signal selected by the phase selecting means and outputting it as a phase signal for phase comparison, and a phase signal output from the shifting means for the horizontal synchronizing signal. Phase change means for storing at a change point and phase comparison means for comparing a reference clock with a phase signal in which an output edge at a specific stage of the oscillation means is synchronized with an edge of a horizontal synchronizing signal synchronized with a reference clock Features that phase selection is executed when the horizontal sync signal is active and that the phase signal selected or shifted after selection is stored when it is inactive And phase selector. 5. A reference clock and an oscillating means for outputting a plurality of signals having the same frequency and different phase as the reference clock, and one phase of an inverted / non-inverted output after latching each output signal of the oscillating means. Phase selecting means for selecting a signal, shift means for shifting the phase signal selected by the phase selecting means and outputting it as a phase signal for phase comparison, and a phase signal output from the shifting means for the horizontal synchronizing signal. Phase change means for storing at a change point and phase comparison means for comparing a reference clock with a phase signal in which an output edge at a specific stage of the oscillation means is synchronized with an edge of a horizontal synchronizing signal synchronized with a reference clock A phase selection device characterized in that the stored phase signal for phase comparison is not updated during the image writing period. 6. A reference clock and an oscillating means for outputting a plurality of signals having the same frequency and different phase as the reference clock, and one phase of an inverted / non-inverted output after latching each output signal of the oscillating means. Phase selecting means for selecting a signal, shift means for shifting the phase signal selected by the phase selecting means and outputting it as a phase signal for phase comparison, and a phase signal output from the shifting means for the horizontal synchronizing signal. Phase change means for storing at a change point and phase comparison means for comparing a reference clock with a phase signal in which an output edge at a specific stage of the oscillation means is synchronized with an edge of a horizontal synchronizing signal synchronized with a reference clock A phase selection device characterized by not updating the phase signal for phase comparison when none of the phase signals is selected.