JPS6230467A - Optical scanning device - Google Patents

Abstract

PURPOSE:To make a picture image scanning clock and a recording position indicating signal the same in phase and to improve the quality of picture image by generating the recording position indicating signal synchronizing with output signals of a frequency divider by specified value count of a counter. CONSTITUTION:A counter 41 is initialized by a synchronizing signal from a photosensor, and counts clocks for position control from a frequency divider 12. When the content of the counter 41 became the first and second values that approximately correspond to starting and termination of printing period in each scanning period, output signals of the counter 41 are inputted to J, K terminals of FF 42, and clock CLA is inputted from a frequency divider 24. Accordingly, the FF 42 is set by rising up of the clock CLA after the counter 41 became the first value, and generates the recording position indicating signal, and when it became the second value, set by rising up of the clock CLA. Accordingly, the recording position indicating signal generated by the FF 42 and the picture image scanning clock from a voltage controlled oscillator (VCO) 22 is made the same in phase.

Description

[Detailed description of the invention] (Technical field) The present invention relates to an optical scanning device that does not use an fθ lens.

(Prior art) An optical scanning device scans a surface to be scanned with a light beam,
It is known as a device for writing optical information.

In such optical scanning devices, the light beam is normally deflected at a constant angular velocity by a rotating deflector such as a polygon mirror or a holo scanner. An fθ lens is used. However, since the fθ lens is a special lens and is expensive, there is a desire to avoid using it if possible.

In addition, polygon mirrors in which the scanning angular velocity of the light beam is not constant have recently been proposed (Japanese Patent Application No. 59-27
No. 4324), in such a case, even if an fθ lens is used, the scanning speed will not be constant, so the fθ lens cannot be used in such a case.

The image scanning clock is a clock signal for turning on and off the scanning light beam during optical scanning, and its frequency fK
is given by 1/T, where T is the time allocated to writing information for one pixel. If the fθ lens is not used, the scanning speed of the surface to be scanned by the scanning light beam will not be constant, so it is better to keep the frequency fx of the image scanning clock constant.

Distortion will occur in the writing of information.

For example, in FIG. 4, reference numeral 30 indicates a photoconductive photoreceptor as a scanned object, reference numeral 32 indicates a polygon mirror for deflecting the light beam L at a constant angular velocity, and reference numeral 34 indicates a photoconductor for deflecting the light beam L at a constant angular velocity. A focusing lens is shown for focusing onto the scanning plane. The light beam L is generally laser light from a gas laser or a semiconductor laser. If the distances n and h are selected as shown in FIG. 4, then h=Q -tar+O The angular velocity of the polygon mirror 32 is ω. (constant). Assuming that the scanning area length is <28 as shown in the figure and H+h=h', then the following is true. Now, assuming that there is one pixel of 2n within this scanning area length 2H, the scanning speed Vn at the nth pixel counted from the scanning start side on the left side of the scanning area in FIG. 4 is. Here, d is one pixel width. By definition, the frequency fg of the image scanning clock is as follows. Therefore, the image scanning clock frequency fg.

By changing each pixel according to equation (1), optical scanning can be realized without using an fθ lens and without causing distortion in writing information.

For example, an image scanning clock generator is an oscillator.

It is composed of a first frequency divider, an up/down counter, a control circuit, and a phase-locked loop circuit.

The phase-locked loop circuit will be abbreviated as PPL below.

An oscillator generates a reference clock. The frequency of this reference clock is hereinafter referred to as fo. fo is of course a constant.

The first divider divides the frequency of the reference clock.

Generates a position control clock.

The up/down counter (hereinafter abbreviated as U/D counter) switches the division ratio N of the first division device.

Of course, N is a natural number.

The control circuit has the following functions. The scanning area is divided in advance into K blocks BLi (i=1 to K), and a predetermined finite number sequence ML (i=1 to K) is divided into K blocks BLi (i=1 to K).
), the i-th block BLi (i = 1~
K), for each Mi pulse of the position control clock,
The U/D counter is driven to realize stepwise switching of the frequency division N over the entire scanning area. That is,
If the initial value of the frequency division ratio N is No, then the position control bronze f.

The frequency of the second block is initially -, but it becomes N in the first block BLI.

When this position control block counts M1 pulses, the control circuit switches the division ratio of the first frequency divider from No to N1 (=No+ΔN) via the U/D counter.

Then, the frequency O of the 1-position control clock becomes -. When the clock of this new frequency is counted i M1 pulses, the frequency division ratio N1 to N
Switch to 2. This is repeated n1 times. Next, in the second block BL2, the position control block M
Switching the division ratio every 2 pulses is repeated n2 times. This process is performed for each block. In the i-th block BLi, switching of the frequency division ratio is performed n1 times every Mi pulse of the position control clock.

The PLL circuit includes a one-phase detection circuit, a low-pass filter, a second frequency divider, and a voltage-controlled oscillator. The second frequency divider has a fixed frequency division ratio M.

This PLL circuit generates an image scanning clock whose frequency changes continuously in response to stepwise changes in the frequency of the 1-position control clock.

This image scanning clock generating device will be described below with reference to the drawings.

In FIG. 2, the one-phase detection circuit 18. Low pass filter 20. The voltage controlled oscillator 22 and the second frequency divider 24 have P
It constitutes an LL circuit.

The reference clock of frequency fo generated from the oscillator 10 is divided by the first divider 12 to obtain the frequency f.

The signal becomes a position control clock of 1-2, and is input to the control circuit 16 and the phase detection circuit 18 of the PLL circuit.

The phase detection circuit 18 uses this position control clock.

The phase of the clock CLA input from the frequency divider 24 is compared, and the phase difference is output to the low-pass filter 20 as a pulse signal. When the information on the phase difference is input to the voltage controlled oscillator 22 via the low-pass filter 20, the oscillator 22 outputs a clock having a frequency corresponding to the output voltage of the low-pass filter 20.

This clock becomes the image scanning clock. The image scanning clock is frequency-divided by the frequency divider 24, applied as a clock CLA to the phase detection circuit 18, and compared in phase with the position control clock.

Now, in the PLL circuit, the frequency of the clock emitted from the voltage-controlled oscillator 22 does not change when there is no change in the phase difference between the clock CLA whose phase is compared in the phase detection circuit 18 and the position side - main clock. . Such a state will be referred to as an equilibrium state of the PLL circuit.

For example, in the balanced state of the PLL circuit, the position control O Assuming that the lock frequency is -, then f.

Since the frequency of the clock CLA is also -, in this state, the f of the clock emitted from the voltage controlled oscillator 22
K is.

It is. In this state, the frequency division ratio of the frequency divider 12 is changed from N to N'
When switching to , the frequency of the position control clock becomes fo・-
Therefore, a phase difference N' occurs between the clock CLA and the clock CLA. Therefore, the frequency fx of the output clock of the voltage controlled oscillator 22 changes accordingly, but this frequency f
The change in g occurs continuously and changes by the frequency fK.

Therefore, by changing the frequency division ratio N of the frequency divider 12 stepwise, the frequency fK of the image scanning clock can be changed continuously.

Now, the control circuit 16 controls a clock CK for outputting a preset value of the frequency division ratio in the frequency divider 12 from the 0/D counter 14, a signal EN for enabling the U/D counter 14 to count, and an up/down mode. A signal U/D is issued to determine the

In the up-down mode, the signal U/D is generated so as to switch from the up mode (or down mode) to the down mode (or up mode) near the extreme value of the scanning speed.

When the clock C is input, the U/D counter 14 updates the preset value and switches the division ratio of the frequency divider 12.

As mentioned above, the clock CK is generated by a finite number sequence Mi (i=1 to K) for each block BLi (i=1 to K).
K). That is, Mi and ni are set in advance for each block, and in the i-th block BLi, the clock CK is generated from the control circuit 16 every time Mi pulses of the position control clock are input. CK is n in this block BLi
It occurs i times.

The number of blocks, Mi, and ni values are the voltage controlled oscillator 2.
The frequency fg of the image scanning clock generated from 2 is set so as to closely approximate the frequency change 1 caused by the change in scanning speed, for example, equation (1). This is nine.

It is determined experimentally or theoretically depending on the design conditions.

FIG. 5 shows an example of a stepwise change in the clock f'g due to a change in the ideal image scanning clock fK (curve 4-1) and switching of the frequency division ratio. The numbers 5, 6, 10, and 16 below the stepwise frequency change are Ml, M2, and M2, respectively, with the right end of Figure 1 as the scanning start side. Compatible with M3° and M4. As can be seen from the figure, n1=6°n2=9. n
3 = 3. n4=5. This figure shows only the right half of the symmetric figure, with MS=10. n5=3.

M6=6. n6=9. M7=5. n7=6. As can be seen from this figure, the block BLi is an area in which a continuous curve of the frequency fg is linearly approximated, and within each block, the width of the steps is equal. Clock f'' corresponds to M times the position control clock. Clock f''
itself changes in a step-like manner.

The frequency of the actual image scanning clock changes continuously due to the action of the PLL circuit, and closely approximates the curve 4-1.

FIG. 3 shows an explanatory timing diagram of the apparatus shown in FIG. From top to bottom: synchronization signal, scanning speed f.

degree 1 division ratio N, frequency of position control clock - 1. Frequency fK of image scanning clock. Since the up/down mode of the U/D counter 14 is switched near the extreme value of the scanning speed, the frequency division ratio N, fo/N, and fk are all symmetrical with respect to the position near the extreme value.

The synchronization signal is the output of the optical sensor shown at 36 in FIG. 4, and the first frequency divider 12 is initialized by this synchronization signal. The synchronization signal is also applied to the control circuit 16.

The signal EN causes the counter operation to be performed with a delay of a predetermined time Ta after receiving the synchronization signal, and after scanning the print area,
The counter operation is ended after a delay of Tb time.

Upon completion of the counter operation, the division ratio N is fixed to the initial value.

The optical scanning device further includes a circuit that generates a recording position instruction signal, and this circuit is initialized by a synchronization signal from the optical sensor 36, counts the position control clock from the frequency divider 12, and sets the count value to a certain value. A recording position instruction signal is generated at a time when the value becomes a different value. This recording position instruction signal and the image scanning clock are sent to an external device, and this external device sends out an image signal in synchronization with the image scanning clock when the recording position instruction signal is input. This image signal is applied to the modulation means to modulate the light beam L, turning on/off a semiconductor laser that generates the light beam, for example, and forming a latent image on the photoreceptor 30.

However, in the above optical scanning device, the synchronization signal from the optical sensor 36 varies due to the rotational deflector 32, and the position control clock from the frequency divider 12 and the clock C from the frequency divider 24
Since the phase with the LA is shifted, the phase of the image scanning clock and the recording position instruction signal is no longer aligned, and a part of the image signal may be lost, resulting in a decrease in image quality.

(Objective) An object of the present invention is to provide an optical scanning device that can improve image quality by aligning the phases of an image scanning clock and a recording position instruction signal.

(Structure) The present invention includes a counter that is initialized by a synchronization signal from an optical sensor and counts a position control clock, and a PL for generating an image scanning clock by counting a predetermined value of this counter.
means for generating a recording position instruction signal in synchronization with the output signal of the frequency divider in the L circuit;
A recording position instruction signal that is in phase with the image scanning clock generated in the circuit is generated.

Next, one embodiment of the present invention will be described.

In this embodiment, as shown in FIG.
1 and a JK flip-flop 42.

The counter 41 is initialized (reset) by a synchronization signal from the optical sensor 36 and counts the position control clock from the 1-station divider 12. The flip-flop 42 operates when the contents of the counter 41 reach a first value and a second value, respectively, corresponding to the beginning and end of the printing period (the period in which a latent image is formed on the photoreceptor 30) within each scanning period. The output signal of the counter 41 is input to the terminal of J, and the clock CLA is input from the frequency divider 24 to the terminal of the flip-flop 42.
is set at the rising edge (or falling edge) of the clock CLA after the contents of the counter 41 reaches the first value, and generates a recording position instruction signal, and when the contents of the counter 41 reaches the second value. Thereafter, it is reset at the rising edge (or falling edge) of the clock CLA. Therefore, the recording position instruction signal generated by the flip-flop 42 is aligned in phase with the image scanning clock from the voltage controlled oscillator 22.

The recording position instruction signal and the image scanning clock are sent to an external device, and when the recording position instruction signal is input, the external device sends an image signal to this embodiment in synchronization with the image scanning clock, and the modulation means The light beam L is modulated by the image signal.

(Effects) As described above, according to the present invention, the phases of the image scanning clock and the recording position instruction signal can be aligned, so that partial loss of the image signal can be eliminated and the image quality can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a part of an embodiment of the present invention, FIG. 2 is a block diagram showing an example of an image scanning clock generation device in an optical scanning device, and FIG. 3 is a timing diagram of the image scanning clock generation device. 4 is a plan view showing an example of the optical scanning device, and FIG. 5 is a diagram for explaining the optical scanning device. 41...Counter, 42...Flip-flop.

Claims (1)

[Claims] This is an optical scanning device that deflects a light beam with a rotating polygon mirror and scans the surface to be scanned with the light beam without using an fθ lens, and includes an oscillator that generates a reference clock and a position control device that divides the frequency of the reference clock. a phase-locked loop circuit that generates an image scanning clock using the position control clock; and a control means for changing the frequency division ratio of the first frequency divider stepwise to continuously change the frequency of the image scanning clock according to the scanning speed of the light beam;
an optical sensor that detects the light beam outside the image scanning area;
In an optical scanning device having means for modulating the light beam by obtaining an image signal in synchronization with the image scanning clock based on a recording position instruction signal, the position control clock is initialized by a synchronization signal from the optical sensor. An optical scanning device comprising: a counter for counting a predetermined value; and means for generating the recording position instruction signal in synchronization with the output signal of the second frequency divider when the counter counts a predetermined value.