JPS6230466A - Regulating method for output of semiconductor laser - Google Patents

Abstract

PURPOSE:To eliminate unevenness of exposure due to change of scanning speed by providing an amplifier behind a D/A converter and adjusting the gain to optimize variation of output intensity of a semiconductor laser due to output of the A/D converter. CONSTITUTION:Output of a D/A converter 44 is amplified by an amplifier 59 and applied to a semiconductor laser driving circuit 45 through an arithmetic unit 57. The circuit 45 changes driving current of a semiconductor laser 42 according to an output signal of the arithmetic unit 57. A picture image scanning clock generator 43 controls a digital value setting circuit 41 to make output of a convertor 44 a value that does not contribute the circuit 45 when power setting of the laser 42 is made. When power setting is not made, output of a D/A converter 56 is retained, and driving current of the laser 42 is changed according to change of scanning speed by output of the convertor 44. Intensity of output of the laser 42 is controlled to a fixed value by power setting, and the value is adjusted by changing reference signal Vref. If change of output intensity of the laser 42 caused by output of the circuit 41 is appropriate, unevenness of exposure due to variation of scanning speed is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a semiconductor laser output adjustment method in an optical scanning device that does not use an fθ lens.

(Prior art) An optical scanning device scans a surface to be scanned with a light beam,
It is known as a device for writing optical information or reading image information.

In such optical scanning devices, the light beam is normally deflected at a constant angular velocity by a rotating deflector such as a polygon mirror or a holo scanner. An fθ lens is used. However, since the fθ lens is a special lens and is expensive, there is a desire to avoid using it if possible.

In addition, polygon mirrors in which the scanning angular velocity of the light beam is not constant have recently been proposed (Patent Application No. 59-2
No. 74324), in such a case, even if an fθ lens is used, the scanning speed will not be constant, so the fθ lens cannot be used in such a case.

The image scanning clock is a clock signal for turning on and off the scanning light beam during optical scanning, and its frequency fk
is given by 1/T, where T is the time allocated to reading or writing information for one pixel. If an fθ lens is not used, the scanning speed of the surface to be scanned by the scanning light beam will not be constant, so the frequency fk of the image scanning clock
If it is kept constant, distortion will occur in the writing and reading of information.

For example, in FIG. 4, reference numeral 30 indicates a photoconductive photoreceptor as a scanned object, reference numeral 32 indicates a polygon mirror for deflecting the light beam L at a constant angular velocity, and reference numeral 34 indicates a photoconductor for deflecting the light beam L at a constant angular velocity. The light beam L, which represents a condensing lens for focusing onto the scanning surface, is generally laser light from a gas laser or a semiconductor laser. If the distances a and b are selected as shown in FIG. 4, then h=Ω・tanθ The angular velocity of the polygon mirror 32 is ω. (constant), the scanning area length is <2H as shown in the figure, and H+h=h'. Now, assuming that there are 2n pixels in this scanning area length 2H, the scanning speed Vn at the nth pixel counting from the scanning start side on the left side of the scanning area in FIG. 4 is t, where d is one pixel wide. By definition, the frequency fk of the image scanning clock is - for n.

becomes. Therefore, by changing the image scanning clock frequency fk for each pixel according to equation (1), optical scanning can be realized without using an fθ lens and without causing distortion in reading or writing information. However, since the scanning speed of the polygon mirror 32 is not constant, the amount of exposure in the scanning area changes in the scanning direction, resulting in uneven exposure. Therefore, a method can be considered to eliminate the exposure unevenness by correcting the output intensity of the semiconductor laser according to the change in the scanning speed. However, in this method, even if the amount of correction of the output intensity of the semiconductor laser deviates slightly, the exposure unevenness cannot be sufficiently eliminated.

(Objective) An object of the present invention is to provide a method for adjusting the output direction of a semiconductor laser, which can improve the above-mentioned drawbacks and sufficiently eliminate exposure unevenness.

(Structure) The present invention is an optical scanning device in which a surface to be scanned is scanned by a rotary deflector with modulated light from a semiconductor laser without using an fθ lens. an image scanning clock generator that generates an image scanning clock that changes automatically; and a digital value setting circuit that generates a digital value for changing the output intensity of the semiconductor laser in accordance with changes in the scanning speed of the scanned surface. In an optical scanning device having a digital/analog converter that converts the output value of the digital value setting circuit into an analog value and changes the current of the semiconductor laser according to the analog value, a The present invention is characterized in that an amplifier is provided, and the gain of the amplifier is adjusted so that the change in the output intensity of the semiconductor laser depending on the output value of the digital/analog converter becomes optimal.

Next, an embodiment of an optical scanning device to which the present invention is applied will be described. The image scanning clock generator in this embodiment includes an oscillator, a first divider, and an up/down counter.
, a control circuit, and a phase-locked loop circuit. The phase-locked loop circuit will be abbreviated as PPL below.

An oscillator generates a reference clock. The frequency of this reference clock is hereinafter referred to as fo. fO is of course a constant.

The first frequency divider divides the frequency of the reference clock.

Generates a position control clock.

The up/down counter (hereinafter abbreviated as U/D counter) switches the frequency division ratio N of the first frequency divider. Of course, N is a natural number.

The control circuit has the following functions. The scanning area is divided in advance into K blocks BLi (i=1 to K), and a predetermined finite number sequence Mi (i=1 to K) is divided into K blocks BLi (i=1 to K).
), the i-th block BLi (i=1 to K)
Then, the U/D counter is driven every Mi pulse of the position control clock to realize stepwise switching of the frequency division N over the entire scanning area. That is, if the initial value of the division ratio N is NO, the frequency fO of the position control block is initially -, but it is N in the first block BLI.

When the position control block counts M1 pulses, the control circuit switches the frequency division ratio of the first frequency divider from NO to N□C:NO+ΔN) via the U/D counter. Then, the frequency f of the position control clock.

becomes -. The clock with this frequency becomes the M1 pulse. When M1 pulses of the clock of this new frequency are counted, the frequency division ratio is further switched from N to N2, and this process is repeated n1 times.

Subsequently, in the second block BL2, switching the frequency division rate every M2 pulse of the 1-position control block is repeated n2 times. This process is performed for each block. In the i-th block BLi, switching of the frequency division ratio is performed ni times for every Mi pulse of the position control clock.

The PLL circuit includes a phase detection circuit, a low-pass filter, a second frequency divider, and a voltage-controlled oscillator. The second frequency divider has a fixed frequency division ratio M.

This PLL circuit generates an image scanning clock whose frequency changes continuously in response to stepwise changes in the frequency of the position control clock.

This image scanning clock generator will be explained below with reference to the drawings.

In FIG. 2, a 1-phase detection circuit 18, a low-pass filter 20, a voltage-controlled oscillator 22. The second frequency divider 24 is PL
It constitutes an L circuit.

The reference clock of frequency fo generated from the oscillator 10 is divided by the first frequency divider 12 to obtain the frequency f.

It becomes a position control clock of several times, and is input to the control port 16 and the phase detection circuit 18 of the PLL circuit.

The phase detection circuit 18 compares the phase of this position control clock and the clock CLA input from the frequency divider 24,
A low-pass filter 20 uses the phase difference as a pulse signal.
Output to. When the information on the phase difference is input to the voltage controlled oscillator 22 via the low-pass filter 20, the oscillator 22 outputs a clock having a frequency corresponding to the output voltage of the low-pass filter 20.

This clock becomes the image scanning clock. The image scanning clock is frequency-divided by the frequency divider 24, applied as a clock CLA to the phase detection circuit 18, and compared in phase with the position control clock.

Now, in the PLL circuit, the frequency of the clock emitted from the voltage controlled oscillator 22 does not change when there is no change in the phase difference between the clock CLA whose phase is compared in the phase detection circuit 18 and the position control clock. Such a state will be referred to as an equilibrium state of the PLL circuit.

For example, in the balanced state of a PLL circuit, f for position control.

Assuming that the lock frequency is -, then the frequency of the fO clock CLA is also -, so in this state, the fO clock generated from the voltage controlled oscillator 22
k is N N . In this state, the frequency division ratio of the frequency divider 12 is changed from N to N'
When switching to , the frequency of the position control clock is generated.

Accordingly, the frequency fk of the output clock of the voltage controlled oscillator 22 changes accordingly, but this change in frequency fk occurs continuously and monotonously changes at one frequency.

Therefore, by changing the frequency division ratio N of the frequency divider 12 stepwise, the frequency fk of the image scanning clock can be changed continuously.

Now, the control circuit 16 includes a clock CK for outputting a preset value of the frequency division ratio in the frequency divider 12 from the U/D counter 14, a signal EN for enabling the U/D counter 14 to count, and an up/down mode. A signal U/D is issued to determine the

In the up-down mode, the signal U/D is generated so as to switch from the up mode (or down mode) to the down mode (or up mode) near the extreme value of the scanning speed.

When the clock C is input, the U/D counter 14 updates the preset value and switches the frequency division ratio of the 1 frequency divider 12.

As mentioned earlier, the clock GK is generated by a finite number sequence Mi (i = 1 to K) for each block BLi (i = 1 to K).
1 to K). Namely.

Mi and ni are set in advance for each block, and in the i-th block BLi, a clock CK is generated from the control circuit 16 every time Mi pulses of the position control clock are input. , occurs ni times in this block BLi.

The number of blocks, Mi, and ni values are the voltage controlled oscillator 2.
The frequency fk of the image scanning clock generated from 2 is set so as to closely approximate the frequency change accompanying the change in scanning speed, for example, equation (1). This is determined experimentally or theoretically depending on design conditions.

FIG. 5 shows an example of an ideal image, a stepwise change in the clock f' due to a change in the image scanning clock fk (curve 4-1) and a switching of the frequency division ratio. The numbers 5, 6, and 10.16 below the change are Ml, M2, and M2, respectively, with the right end of the figure as the scanning start side. Compatible with M3゜■. As you can see from the figure, n1=6゜n2=9
, n3=3, n4=5. This figure shows only the right half of the symmetric figure, with MS=10. n5=
3.

M6= 6, n6= 9, M7= 5, n7=
It is 6. As can be seen from this figure, the block BLi is an area in which a continuous curve of frequency fk is linearly approximated, and the width of the steps within each block is equal. The clock f' corresponds to M times the position control clock. The clock f' itself changes in one step, but the PLL
Due to the action of the circuit, the frequency of the actual image scanning clock changes continuously and closely approximates the curve 4-1.

FIG. 3 shows an explanatory timing diagram of the apparatus shown in FIG. From the top, the synchronizing signal, scanning method O degree, branching ratio N1, frequency of position control clock - frequency fk of image scanning clock are shown. Since the up/down mode of the U/D counter 14 is switched near the extreme value of the scanning speed, the 1 frequency division ratio N, fo/N, and fk are all symmetrical with respect to the position near the extreme value.

The synchronization signal is the output of the optical sensor shown at 36 in FIG. 4, and the first frequency divider 12 is initialized by this synchronization signal. The synchronization signal is also applied to the control circuit 16.

The signal EN causes the counter operation to be performed with a delay of a predetermined time Ta after receiving the synchronization signal, and after scanning the print area,
The counter operation is ended after a delay of Tb time. Upon completion of the counter operation, the frequency division ratio N is fixed to the initial value.

FIG. 1 shows the circuit configuration of this embodiment.

The digital value setting circuit 41 generates a digital value for eliminating uneven exposure by changing the output intensity of the semiconductor laser 42 according to changes in the light beam scanning speed on the surface to be scanned, and is, for example, a U/D counter. is used.

This U/D counter 411 is used by the control circuit 1 in the image scanning clock generator 43 as shown in FIG. 6(a).
6 to the U/D counter 14, the clock CK, the enable signal EN, and the up/down mode signal U/D are applied to perform U/D counting and generate a digital value according to the change in the light beam scanning speed. Further, the digital value setting circuit 41 uses an adder (or subtracter) as shown in FIG. 6(b) to add (subtract) the output of the U/D counter 14 and a predetermined value. It's okay. The output of the digital value setting circuit 41 is converted into an analog value by a digital/analog converter 44, and becomes a value corresponding to a change in the light beam scanning speed as shown in FIG.

On the other hand, as shown in FIG. 4, the laser beam emitted forward from the semiconductor laser 42 is focused by the condenser lens 34, deflected by the polygon mirror 32, and condensed on the surface charged by the charger of the photoreceptor 30. The imaged spot is repeatedly moved by the rotation of the polygon mirror 32, and at the same time, the photoreceptor 30 is rotated.

An optical sensor 36 is provided outside the information writing area, detects the laser beam deflected by the polygon mirror 32, and generates a synchronization signal. The semiconductor laser drive circuit 45 receives a modulation signal in synchronization with the image scanning clock and drives the semiconductor laser 42 with this modulation signal. Therefore, the laser beam modulated with the modulation signal is irradiated onto the photoreceptor 30 to generate electrostatic charge. A latent image is formed. This electrostatic latent image is developed by a developing device and transferred onto paper or the like by a transfer device.

The laser beam emitted backward from the semiconductor laser 42 enters a photodetector 46 consisting of a photodiode,
Photodiode 46 outputs a current proportional to the intensity of the laser beam. This current is converted into a voltage by an amplifier 47 and compared with a reference voltage V ref by a comparator-8. The output voltage of the comparator 48 becomes a high level or a low level depending on the magnitude relationship of the surface input voltage of the comparator 48, and controls the counting mode of the up/down counter 49.

For example, when the intensity of the laser beam from the semiconductor laser 42 is weaker than the reference value, the output of the comparator 48 becomes a low level, and the up/down counter 49 enters a state in which it operates as an up counter. The edge detection circuit 50 receives a frame synchronization signal FSYNC which becomes low level in recording mode.
The rising edge of is detected, and the detection signal is sent to the OR circuit 51.
The frame synchronization signal FSYNC is passed through the AND circuit 52.
The AND is taken. Flip-flop 53 is set at the beginning of standby mode by the output signal of AND circuit 52 to produce an output signal, which is ANDed with the non-photoreceptor scanning signal from the signal processing circuit in AND circuit 54. The up/down counter 49 is enabled by the output signal of the AND circuit 54, and counts up/down the clock pulses from the clock pulse generator 55. This up/down counter-49
The count output is converted into an analog quantity by the digital/analog converter 56 and applied to the semiconductor laser drive circuit 45 via the arithmetic unit 57. The semiconductor laser drive circuit 45 drives the semiconductor laser 42 by the modulation signal from the signal processing circuit. However, the drive current is digitally/
It is changed according to the output of the analog converter 56. Therefore, as the count value of the up/down counter 49 gradually increases, the intensity of the laser beam from the semiconductor laser 42 gradually increases, and the output voltage of the amplifier 47 increases. When the photoconductor is scanned, the non-photoconductor scanning signal is lost, the AND circuit 54 is turned off, and the up/down counter 4 is turned off.
9 becomes disabled and the semiconductor laser 4
2 is not driven when scanning the photoreceptor in a standby state, and the power setting of the semiconductor laser 42 is interrupted if it is not yet completed. Then, when scanning a non-photoreceptor, the semiconductor laser 42 is again used.
power set is restarted.

After that, when the output of the comparator 48 is inverted from low level to high level, the edge detection circuit 58 detects the rising edge of the output of the comparator 48 and resets the flip-flop 53 via the OR circuit 60, thereby inverting the up/down counter. -49
returns to the disabled state.

Therefore, the up/down counter 49 holds the count value, and therefore the magnitude of the driving current of the semiconductor laser 42 is held as it is. Furthermore, when the up/down counter 49 is enabled by the output signal of the AND circuit 54, if the output of the comparator 48 is at a high level (if the output intensity of the semiconductor laser is strong), the up/down counter 49 will go down. It operates as a counter and the count value is decreased by the clock signal from the clock pulse generator 55. Therefore, the output of the digital/analog converter 56 decreases, the drive current of the semiconductor laser 42 decreases, and the output of the amplifier 47 decreases. Then, when the output of the amplifier 47 becomes smaller than the reference voltage V ref and the output of the comparator 48 is inverted from high level to low level, the edge detection circuit 58 detects the falling edge of the output of the comparator 48 and switches the flip-flop 53. and returns the up/down counter 49 to the disabled state. Therefore, the up/down counter 49 holds the count value, and the magnitude of the driving current of the semiconductor laser 42 is maintained as it is. If the edge detection circuit 58 is configured to disable the up/down counter 49 only when the output of the comparator 48 is inverted from a low level to a high level, the output of the comparator 48 will be at a low level. When the output of the comparator 48 is inverted from a low level to a high level while the up/down counter 49 is enabled, the up/down counter 49 becomes disabled and holds the count value. If the output of the comparator 48 goes from high to low when the output of the comparator 48 is high and the up/down counter 49 is enabled, the up/down counter 49 continues to be disabled and performs the comparison. The output of the circuit 48 causes it to operate as an up counter. When the driving current of the semiconductor laser 42 increases and the output of the comparator 48 is reversed from a low level to a high level, an edge detection circuit 58 detects the rising edge and outputs the up/down counter 4.
9 is disabled and its count value is held.

The output control timing generator 61 also outputs a frame synchronization signal F.
Operates in standby mode by SYNC, with constant cycle T
By generating an output control timing signal and outputting it to the OR circuit 51, the power of the semiconductor laser 42 is set at regular intervals.

Note that the up/down counter 49 operates as a down counter when the output of the comparator 48 is at a low level.
8 may operate as an up/down counter at a high level, and the count value and the driving current of the semiconductor laser 42 may be inversely proportional to each other.

The output of the digital/analog converter 44 is amplified by an amplifier 59 and applied to the semiconductor laser drive circuit 45 via the arithmetic unit 57. change. In the image scanning clock generator 43, the control circuit 16 uses the output signal of the flip-flop 53 to set the output of the digital/analog converter 44 to a value that does not contribute to the semiconductor laser drive circuit 45 when setting the power of the semiconductor laser 42. Controls the digital value setting circuit 41.

When the power of the semiconductor laser 42 is not set, the output of the digital/analog converter 56 is held, and the drive current of the semiconductor laser 42 changes according to the change in scanning speed by the output of the digital/analog converter 44. The output intensity of the semiconductor laser 42 is controlled to a constant value by the power set, and the value can be adjusted by varying the reference signal Vref. Furthermore, if the output intensity change of the semiconductor laser 42 due to the output of the digital value setting circuit 41 is appropriate, exposure unevenness due to a change in scanning speed will be eliminated. During production, etc., a worker turns on the switch 62 to set the semiconductor laser output intensity modulation mode, and determines the maximum value of the amount of change in the output intensity of the semiconductor laser 42 due to the output of the digital value setting circuit 41 (that is, the minimum output intensity). is measured with a power meter and adjusted by varying the gain of the amplifier 59 so that this maximum value becomes an appropriate value. In this case, the control circuit 1 in the image scanning clock generator 43
6 forcibly resets the flip-flop 53 via the OR circuit 60 in response to the ON signal from the switch 62, thereby disabling the up/down counter 49. Therefore, the count value of the up/down counter 49 is held.

The output intensity of the semiconductor laser 42 decreases from the intensity corresponding to the count value in accordance with the output of the digital value setting circuit 41.

(Effects) As described above, according to the present invention, an optical scanning device that does not use an fθ lens generates a digital value for changing the output intensity of a semiconductor laser in accordance with changes in the scanning speed of the scanned surface. An optical scanning device having a digital value setting circuit that converts the output value of the digital value setting circuit into an analog value and a digital/analog converter that changes the current of the semiconductor laser according to the analog value,
An amplifier is provided after the digital/analog converter,
Since the gain of this amplifier is adjusted so that the change in the output intensity of the semiconductor laser depending on the output value of the digital/analog converter is optimized, it is possible to sufficiently eliminate exposure unevenness due to changes in scanning speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the circuit configuration of an embodiment of an optical scanning device to which the present invention is applied, FIG. 2 is a block diagram showing an image scanning clock generator in the embodiment, and FIG. Timing chart. FIG. 4 is a plan view showing an example of an optical scanning device, FIG. 5 is a diagram for explaining the above embodiment, and FIGS. 6(a) and (b) are block diagrams showing each side of the digital value setting circuit. , FIG. 7 is a timing chart of the above embodiment. 41... Digital value setting circuit, 43... Image scanning clock generator, 44... Digital/analog converter, 59... Amplifier, 60... Switch.ゐC cause (a) Outside 7 Figure

Claims (1)

[Claims] An optical scanning device that scans a scanning surface using a rotating deflector with modulated light from a semiconductor laser and does not use an fθ lens,
an image scanning clock generator that generates an image scanning clock whose frequency changes continuously according to changes in the scanning speed of the surface to be scanned; and an image scanning clock generator that changes the output intensity of the semiconductor laser according to changes in the scanning speed of the surface to be scanned. a digital value setting circuit that generates a digital value to set the output value, and a digital/analog converter that converts the output value of the digital value setting circuit into an analog value and changes the current of the semiconductor laser according to the analog value. In an optical scanning device having
An amplifier is provided after the digital/analog converter,
A semiconductor laser output adjustment method, comprising adjusting the gain of the amplifier so that the change in the output intensity of the semiconductor laser depending on the output value of the digital/analog converter is optimized.