JPH0523662B2 - - Google Patents

Description

[Detailed description of the invention] (Technical field) The present invention relates to an optical scanning device.

(Prior Art) An optical scanning device that uses a rotating deflector such as a rotating polygon mirror or a hologram scanner to deflect modulated light from a semiconductor laser is well known. A rotary deflector generally deflects a light beam at a constant angular velocity, so in order to keep the scanning speed on the surface to be scanned constant, an f-theta lens (as widely known among those skilled in the art, etc.) is generally used. A lens that has an optical function that uniformizes the speed of light scanning on the scanned surface by a deflected light beam that is deflected at an angular velocity.)
is used. However, fθ lenses are special lenses and are expensive to manufacture. Therefore, there is a desire to eliminate the use of an fθ lens if possible. In addition, recently, special polygon mirrors in which the scanning angular velocity of the light beam is not constant have been proposed (Japanese Patent Application No. 59-274324), and in such cases,
Even if an fθ lens is used, the scanning speed will not be constant, so an fθ lens cannot be used.

In view of these circumstances, optical scanning devices that perform optical scanning without using an fθ lens have recently been designed. For example, FIG. 5 shows an example of such an optical scanning device.

The light flux enters a rotating polygon mirror 82 which is a rotating deflector via a lens 80, is reflected by one of its reflecting surfaces, enters a photoconductive photoreceptor 84, and is directed onto the photoreceptor by the action of the lens 80. focus on. When the rotating polygon mirror 82 is rotated at a constant speed in the direction of the arrow, the light beam is deflected from the left to the right in FIG. Light scan. Note that reference numeral 86 indicates a light receiving element, and this light receiving element 86 is used to synchronize the starting point of optical scanning. As the rotating polygon mirror 82 rotates, the reflecting surface that reflects the light beam is switched, and the deflection, that is, the optical scanning is periodically repeated.

Incidentally, when optical scanning is performed, a clock having a frequency fk given by 1/T is called an image scanning clock, where T is the time allocated to writing information for one pixel.

In an optical scanning device that does not use an fθ lens, the scanning speed of the scanning light on the scanned surface is not constant, so if the frequency fk of the image scanning clock is kept constant, the written information will be distorted. I end up. In order to remove such information distortion, it is necessary to change the frequency fk in accordance with changes in the scanning speed on the surface to be scanned. That is, where the scanning speed is high, the frequency fk of the image scanning clock must be increased accordingly, and where the scanning speed is low, the frequency fk must be decreased accordingly.

In this way, the frequency fk of the image scanning clock is
By changing the scanning speed according to the scanning speed, distortion of the written information image can be effectively reduced.

By the way, as mentioned earlier, the frequency fk is 1
This is the reciprocal of the time T allocated for writing information to a pixel. Therefore, the frequency fk changes over time T
respond to changes in Then, during optical scanning, if the intensity of the scanning light is constant, the amount of light used to write one pixel will vary depending on where the scanning speed is high (time T is short) and where it is low (time T is long). This results in a difference in energy, and when writing by optical scanning, as the scanning speed changes,
The amount of exposure light per pixel changes, and the image density changes in the resulting information image in accordance with the change in scanning speed.

(Purpose) The present invention was made in view of the above information, and effectively reduces distortion of an information image and changes in image density caused by changes in scanning speed in an optical scanning device that does not use an fθ lens. The purpose of the present invention is to provide a novel optical scanning device that can perform the following steps.

(composition) The present invention will be explained below.

In the present invention, the optical scanning device serves as a light source,
Uses a semiconductor laser. The modulated light from the semiconductor laser (modulated with a modulation signal corresponding to the image signal) is deflected by a rotating deflector, that is, a rotating polygon mirror or a hologram scanner, and is used to scan the scanned surface without using an fθ lens. Light scan.

Since the emission intensity of semiconductor lasers is extremely unstable with respect to temperature, the output intensity control circuit
The emission intensity is set to a reference value.

The setting of the light emission intensity to the reference value is performed at a time other than during optical writing scanning. In other words, it may be performed during standby before the start of optical writing scanning for one page, or during the time period other than the optical writing time during each deflection of the scanning light while optical scanning is being performed. The deflection may be performed using a time other than the optical writing time, and the deflection may be performed once every several times of deflection.

As the output intensity control circuit, the one previously proposed by the applicant in Japanese Patent Application No. 16010/1988 can be used.

Further, an image scanning clock frequency control circuit generates an image scanning clock whose frequency changes continuously in response to changes in the scanning speed on the surface to be scanned.

As this image scanning clock frequency control circuit, the one previously proposed by the applicant in Japanese Patent Application No. 60-92960 can be used.

Now, when the emission intensity of the semiconductor laser during optical writing scanning is set to a reference value, a digital reference value signal is obtained from the output intensity control circuit.

On the other hand, in the image scanning clock frequency control circuit,
The frequency division ratio for the reference clock from the oscillator is switched stepwise, and an image scanning clock whose frequency changes continuously is obtained from the phased locked loop circuit accordingly. Each time it is switched, the up/down counter is driven and a digital correction signal is obtained by the digital value setting circuit.

Then, the above-mentioned reference value signal and correction signal are applied to the arithmetic circuit.

The arithmetic circuit is a digital circuit, and arithmetic modulates the applied reference value signal with a correction signal. This arithmetic modulation is performed so that the output signal of the arithmetic circuit becomes a signal that changes stepwise in proportion to the change in scanning speed.

Operations in the arithmetic circuit include addition, subtraction, multiplication,
It can be either division.

In other words, if the correction signal corresponds proportionally to the change in scanning speed, an addition, subtraction or multiplication operation is performed, and if the correction signal and the change in scanning speed correspond inversely to each other, an addition, subtraction or division operation is performed. will be carried out.

The output from the arithmetic circuit is converted into an analog signal by a D/A converter. This analog signal also changes stepwise in proportion to the change in scanning speed. The stepwise change in the analog signal corresponds to the appropriate exposure amount according to the frequency change of the image scanning clock in a good approximation.
It determines the output value of the down counter and the arithmetic expression for the arithmetic circuit.

Then, the semiconductor laser is driven while modulating this analog signal with a modulation signal.

Then, since the above-mentioned analog signal changes stepwise in proportion to the change in scanning speed, the emission intensity of the semiconductor laser, although it changes stepwise, is large at high scanning speeds and is large at low scanning speeds. is small and corresponds quickly to an appropriate exposure amount. Therefore, exposure unevenness caused by frequency changes of the image scanning clock can be effectively reduced.

Hereinafter, description will be given based on specific examples.

FIG. 1 shows an example of a circuit for an optical scanning device of the present invention. In FIG. 1, an image scanning clock frequency control circuit 38 and a digital value setting circuit 4 are shown.
The applicant had previously applied for the patent application in 1984-
This is the same as the output intensity control circuit proposed in No. 16010.

Therefore, with reference to FIG. 1, first, setting of the emission intensity of the semiconductor laser to a reference value and generation of the reference value signal will be explained.

The output from the up/down counter 20 and the output from the digital value setting circuit 40 are applied to the arithmetic circuit 42, and when the above-mentioned emission intensity is set to the reference value (hereinafter referred to as output intensity control). ), the output from the digital value setting control circuit 40 indicates a value that does not contribute to the calculation. Therefore,
During output intensity control, the arithmetic circuit 42
It functions as a multiplier circuit that multiplies the output of the down counter 20 by a factor of 1.

Note that during optical writing scanning, the output of the up/down counter 20 is held. Now, the laser light emitted backward from the semiconductor laser 10 is
The light is illuminated by the photosensor 14. Photo sensor 14
outputs a current proportional to the intensity of the received light,
This current is converted into a voltage by the amplifier 16 and applied to the comparator 18 as a voltage value V _M , and the reference voltage
Compared to Vref. The output voltage of the comparator 18 is
Depending on the magnitude relationship between the voltage V _M and Vref, the level becomes high or low, and the up/down counter 2
0 (hereinafter simply referred to as counter 20). For example, when V _M <Vref, that is, when the output intensity of the semiconductor laser 10 does not reach the reference value, the output of the comparator 18 is at a low level, and the counter 20 is in a count mode in which it operates as an up counter, that is, an up mode. When V _M >Vref, on the other hand, the count mode operates as a down counter, that is, the down mode.

The edge detection circuit 32 uses a frame synchronization signal
The rising edge of FSYNC is detected, and the detected signal passes through an OR circuit 34 and is ANDed with the frame synchronization signal FSYNC in an AND circuit 30.

Flip-flop 28 is set at the beginning of standby mode by the output of AND circuit 30 to produce an output signal, which output signal is output to AND circuit 26.
Then, an AND with the non-scanning signal is taken.

The counter 20 is released from the disabled state by the output signal of the AND circuit 26, and counts up or down the clock pulses from the clock pulse generator 24.

The count output of the counter 20 is sent to the arithmetic circuit 4.
2 to the D/A converter 43,
The signal is converted into an analog signal by the D/A converter 43 and applied to the semiconductor laser drive circuit 12.

The circuit 12 drives the semiconductor laser 10 using a modulation signal, and changes the drive current according to the output from the arithmetic circuit.

Therefore, as the count value of the counter 20 gradually increases (or decreases), the intensity of the laser light from the semiconductor laser 10 gradually increases (or decreases), and the voltage applied to the comparator 18 increases (or decreases).
V _M increases (or decreases) gradually.

When the voltage V _M gradually changes and its magnitude relationship with Vref is reversed, the output of the comparator 18 is also reversed from a low level to a high level (or from a high level to a low level). At this time, edge detection circuit 22 detects the rising (or falling) edge of the output of comparator 18, resets flip-flop 28, and returns counter 20 to the disabled state. Therefore, the counter 20 holds the count value when the output of the comparator 18 is inverted, and therefore,
The magnitude of the driving current of the semiconductor laser 10 is maintained as it is. At this time, substantially V _M =Vref, and the output intensity of the semiconductor laser 10 is set to the reference value set through the reference voltage Vref.
In this manner, the digital signal output from the counter 20 is the reference value signal in a state where the emission intensity of the semiconductor laser 10 is set to the reference value.

Note that the edge detection circuit 22 may be configured to disable the counter 20 only when the output of the comparator 18 inverts from a low level to a high level. In this way, when the output level of the comparator 18 is inverted from a low level to a high level, it is the same as the above case, but when the output level is inverted from a high level to a low level, the following is done. become. That is, when flipping from high level to low level, counter 20
will operate as an up counter while the disabled state is released. Then, when the drive current of the semiconductor laser 10 increases and the output of the comparator 18 is reversed from low level to high level, the edge detection circuit 21 detects the rising edge and disables the counter 20. The count value is held.

Further, the counter 20 operates as a down counter when the output of the comparator 12 is at a low level, and operates as an up counter when the output is at a high level, so that the count value and the driving current of the semiconductor laser 10 are inversely proportional to each other. It's okay.

Note that the output control timing generation circuit 36 operates in standby mode in response to the frame synchronization signal FSYNC, and generates an output control timing signal at a constant cycle and outputs it to the OR circuit 34.
The power setting of the semiconductor laser 10 is performed in constant synchronization.

When scanning the photoreceptor, the AND circuit 26 is turned off when there is no non-scanning signal, the counter 20 is disabled, and the semiconductor laser 10 is turned off.
is not driven during scanning in the standby state, and the power setting of the semiconductor laser 10 is interrupted if it is not yet completed. Then, during non-scanning, the power set is restarted. As described above, when the emission intensity of the semiconductor laser is set to the reference value, the counter 2
A reference value signal is obtained from 0. This reference value signal may change each time a power set is performed, but once a power set is performed, it will not change until the next time.

Next, generation of the correction signal will be explained.

FIG. 2 shows a specific example of the image scanning clock frequency control circuit 38 and digital value setting circuit 40 shown in FIG.

In Figure 2, up/down counter 6
8 and the arithmetic circuit 42 constitute an image scanning clock frequency control circuit, and this control circuit is the same as that previously proposed by the applicant in Japanese Patent Application No. 60-92960. In this image scanning clock frequency control circuit, a phase detection circuit 58, a low pass filter 60, a voltage controlled oscillator 62,
Frequency divider 64 constitutes a phased locked loop circuit (hereinafter referred to as a PLL circuit).

From the image scanning clock frequency control circuit above.
The portion excluding the PLL circuit and the up/down counter 68 constitute the digital value setting circuit 40 in FIG.

First, the function of the image scanning clock frequency control circuit will be briefly explained.

The reference clock of frequency fo generated from the oscillator 54 is divided by the frequency divider 56 to obtain the frequency
It becomes the position control clock for fo/N, and the control circuit 1
6 and the phase detection circuit 58 of the PLL circuit.

The phase detection circuit 58 compares the phases of the position control clock and the clock input from the frequency divider 64, and outputs the phase difference to the low-pass filter 60 as a pulse signal. low pass filter 6
When the information on the phase difference is input to the voltage controlled oscillator 62 through 0, the oscillator 62 outputs a clock having a frequency corresponding to the output voltage of the low-pass filter 60. This clock becomes the image scanning clock. The image scanning clock is frequency-divided by a frequency divider 64, applied as a clock to the phase detection circuit 58, and compared in phase with the position control clock.

The frequency division ratio of the frequency divider 64 is a fixed value, if this is M, and from this frequency divider 64 to the phase detection circuit 58.
When the phase difference between the clock applied to and the position control clock (frequency fo/N) does not change, the frequency fk of the image scanning clock emitted from the voltage controlled oscillator 62 is Mfk=fo.-.

N In this state, change the frequency division ratio of the frequency divider 56 from N to N ₁
When switched to , the frequency of the position control clock becomes fo.
1/N ₁ , and the frequency fk of the image scanning clock changes continuously and monotonically from fo·M/N to fo·M/N ₁ .

Therefore, by stepwise switching the frequency division ratio of frequency divider 56, an image scanning clock whose frequency changes continuously can be obtained.

Now, the control circuit 50 outputs a clock CK for outputting the preset value of the frequency division ratio in the frequency divider 56 from the up/down counter 52 (hereinafter simply referred to as counter 52), a signal EN for canceling the disable state, and an up/down counter 52 (hereinafter simply referred to as counter 52). /Emits signal U/D to set the down mode. Note that the control circuit 50 and the frequency divider 56 include a light receiving element 86 (sixth
A synchronization signal obtained from Fig.) is applied.

In the up/down mode, the signal U/D is generated so that the up mode (or down mode) can be switched to the down mode (or up mode) near the extreme value of the scanning speed.

When the clock CK is input, the counter 52
The preset value is updated to switch the frequency division ratio of the frequency divider 56. The switching width ΔN is constant.

Now, the scanning area where optical scanning is performed is as follows:
Multiple blocks BL1, BL2,..., BLi,...,
BLK, each block BLi (i=1
~K), numerical values Mi and ni (i=1~K) are determined.

In the i-th block BLi, each time the position control clock inputs a Mi pulse to the control circuit 50, the control circuit 50 generates a clock CK, thereby changing the frequency division ratio of the frequency divider 56. ΔN
Switch only. In block Bli, the occurrence of clock CK occurs ni times. Therefore, the block BLi corresponds to Mi·ni position control clocks. Then, while the block BLi is optically scanned, the frequency division ratio changes by ni·ΔN.

The number of blocks K and the values of Mi and ni are the frequencies of the image scanning clock generated from the voltage controlled oscillator 22.
fk is experimentally or theoretically determined depending on the design conditions of the optical scanning device so that fk closely approximates the ideal frequency change accompanying a change in scanning speed.

An example is shown in FIG. In the figure, the curve represents the ideal image scanning clock fko (as a rotating deflector,
A rotating polygon mirror using a special polygon mirror proposed in Japanese Patent Application No. 59-274324 is envisaged. In this rotating polygon mirror, depending on the rotation angle α of the polygon mirror, the deflection angle θ of the light beam satisfies the relationship sin θ=(1−A/R sin α). A and R are morphological constants of the polygon mirror. ), and the stepped graph line indicates the frequency fk ₁ =M/N·fo, respectively. By switching the frequency division ratio N stepwise, the frequency changes stepwise. The numbers 5, 6, 10, and 16 below the broken line _fk1 correspond to M1, M2, M3, and M4, respectively, with the right end of the figure as the scanning start side. As is clear from the figure, n1=6, n2
=9, n3=3, n4=5. This figure shows only half of the symmetric figure, and as is clear from the symmetry, the number of blocks K is 7, M5 = 10, n5 = 3,
M6=6, n6=9, M7=5, n7=6. Further, the switching width ΔN of the frequency division ratio N is 1. As the frequency division ratio is switched stepwise, the image scanning clock changes continuously to closely approximate the ideal frequency change _fk0 . Incidentally, the frequency division ratio N is 69 at both ends of the scanning area and 89 at the center.

The above is a description of the image scanning clock frequency control circuit.

Now, returning to FIG. 2 again, the generation of the correction signal will be explained.

Signals EN, CK, U/ generated in the control circuit 50
At the same time that D is applied to the counter 52, it is applied to an up/down counter 68 (hereinafter simply referred to as counter 68). Therefore, the counter 68 and the counter 52 simultaneously
It is released from the disabled state, performs counting, and switches between up mode and down mode. Therefore, the counter 68 is driven and counts every time the frequency division ratio N with respect to the reference clock from the oscillator 54 is switched in the image scanning clock frequency control circuit, and the counter 68 performs a digital count that changes stepwise according to the count amount. Output a signal.
This signal is a correction signal.

In the example explained above, since the up/down modes of the counters 52 and 68 are the same, this correction signal is large when the scanning speed is high and small when the scanning speed is low, as shown in FIG. .

Therefore, the above-mentioned reference value signal is computationally modulated using this correction signal.

The correction signal and the reference value signal are applied to the arithmetic circuit 42, and the reference signal is arithmetic modulated by the correction signal.

In the example currently being described, the correction signal is a signal that changes in proportion to the magnitude relationship of the scanning speed, as shown in FIG. Multiplying operations that multiply the two, or addition and subtraction that take the sum or difference of both.
By performing subtractive calculations, it is possible to obtain digital signals that change stepwise in proportion to changes in scanning speed.

Therefore, by converting this digital signal into an analog signal using the D/A converter 43 and applying it to the semiconductor laser drive circuit 12, and driving the semiconductor laser while modulating it with a modulation signal, it is possible to reduce the , where the emission intensity of the semiconductor laser is high and the scanning speed is low, the above emission intensity becomes small (however, the change in emission intensity is stepwise), so the non-uniformity of the exposure amount over the scanning direction is effectively reduced. That will happen.

FIG. 3 shows another example of a circuit for obtaining a correction signal. In this example, in the image scanning clock frequency control circuit, the output of the up/down counter 52, which is driven when the frequency division ratio is switched stepwise, is applied to the calculation circuit 70, and is combined with a predetermined value to perform the necessary calculations. A desired correction signal is obtained by performing processing such as addition or subtraction.

In addition, in FIGS. 2 and 3, the mode setting signal is the digital value setting circuit 4 when setting the output intensity.
The digital value setting circuit 40 is controlled so that the output of 0 (FIG. 1) does not contribute to driving the semiconductor laser, and the up/down counter 2 is controlled so that the output of the counter 20 is held during optical writing scanning.
Controls 0.

(Effects) As described above, according to the present invention, a novel optical scanning device can be provided. Since the optical scanning device of the present invention is configured as described above, it is possible to perform optical scanning while effectively removing distortion and density unevenness in a recorded image, even though no fθ lens is used.

In addition, since the correction signal is also generated digitally, the generation circuit can be configured with a low-cost IC.
It is also highly reliable.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a circuit for implementing the present invention, FIG. 2 is a block diagram showing an example of a circuit for generating a correction signal, and FIG. 3 is a block diagram showing an example of a circuit for generating a correction signal. FIG. 4 is a block diagram showing another example of the circuit for generating the correction signal. FIG. 4 is a diagram for explaining the correspondence between the scanning speed and the correction signal. FIG. The figure shown in FIG. 6 is a diagram for explaining the function of the image scanning clock frequency control circuit. 10... Semiconductor laser, 14... Photo sensor.

Claims (1)

[Scope of Claims] 1. An optical scanning device that scans a surface to be scanned by deflecting modulated light from a semiconductor laser with a rotating deflector and without making scanning at a constant speed with an fθ lens, comprising: optical writing; An output intensity control circuit for obtaining a digital reference value signal for setting the emission intensity of a semiconductor laser to a reference value during scanning, an oscillator for generating a reference clock, and a frequency divider for dividing the frequency of the reference clock. an image scanning clock frequency control circuit that generates an image scanning clock whose frequency changes continuously according to changes in the scanning speed on the surface to be scanned; and in this image scanning clock frequency control circuit, the frequency divider A digital value setting circuit that switches the frequency division ratio in stages and obtains a digital correction signal each time the switching occurs; and a digital value setting circuit that receives the reference value signal and correction signal respectively, and converts the reference value signal into a digital signal using the correction signal. an arithmetic circuit for obtaining a signal that changes stepwise in proportion to a change in the scanning speed; An optical scanning device characterized by having a D/A converter that converts into an analog signal for driving a semiconductor laser.