JPS6230213A - Optical scanner - Google Patents

Abstract

PURPOSE:To improve image quality by selecting a signal in synchronization with either the rise or fall of the frequency divider output of an image scan clock generating PLL circuit with the aid of a recording position instructing signal. CONSTITUTION:A counter 41 is initialized (reset) by a synchronizing signal from an optical sensor 36, and counts a position control clock from the frequency divider 12. After the contents of the counter 41 come to the 1st value, a flip-flop 42 is set by the rise of a clock CLA to generate the recording position indicating signal, and after the contents of the counter 41 come to the 2nd value, the flip-flop 42 is reset by the rise of the clock CLA. Accordingly, a switch 45 can select whether the recording position instructing signal is generated by the rise of the clock CLA or by the fall of the clock CLA. The recording position instructing signal and an image scan clock are transmitted to an external device, which transmits a picture signal to a modulating means by synchronizing the picture signal with the image scan clock when the recording position instructing signal is inputted. Then the modulating means modulates a light beam L with the aid of said picture signal.

Description

[Detailed description of the invention] (Technical field) The present invention relates to an optical scanning device that does not use an fθ lens.

(Prior art) An optical scanning device scans a surface to be scanned with a light beam,
It is known as a device for writing optical information.

In such optical scanning devices, the light beam is normally deflected at a constant angular velocity by a rotating deflector such as a polygon mirror or a holo scanner. An fθ lens is used. However, since the fθ lens is a special lens and is expensive, there is a desire to avoid using it if possible.

In addition, polygon mirrors in which the scanning angular velocity of the light beam is not constant have recently been proposed (Japanese Patent Application No. 59-27
No. 4324), in such a case, even if an fθ lens is used, the scanning speed will not be constant, so the fθ lens cannot be used in such a case.

The image scanning clock is a clock signal for turning on and off the scanning light beam during optical scanning, and its frequency fg
is given by 1/T, where T is the time allocated to writing information for one pixel. If the fθ lens is not used, the scanning speed of the surface to be scanned by the scanning light beam will not be constant, so if the frequency fK of the image scanning clock is kept constant, distortion will occur in the writing of information.

For example, in FIG. 4, reference numeral 30 indicates a photoconductive photoreceptor as a scanned object, reference numeral 32 indicates a polygon mirror for deflecting the light beam L at a constant angular velocity, and reference numeral 34 indicates a photoconductor for deflecting the light beam L at a constant angular velocity. The six light beams L indicating a condensing lens for focusing on the scanning surface are generally laser beams from a gas laser or a semiconductor laser. Distance 0. If h is selected as shown in FIG. 4, then h=QIItanθ.The angular velocity of the polygon mirror 32 is ω. (constant). If the scanning area length is <2H as shown in the figure and H+h=h', then the following is true. Now, assuming that there are 2n0 pixels within this scanning area length 2H, the scanning speed Vn at the n-th pixel counted from the scanning start side on the left side of the scanning area in FIG. 4 is. Here, d is one pixel width.The frequency fx of one image scanning clock is as follows from its definition. Therefore, the image scanning clock frequency fx.

By changing each pixel according to equation (1), optical scanning can be realized without using an fθ lens and without causing distortion in writing information.

For example, the image scanning clock generator includes an excavator, a first branch, an up/down counter, a control circuit, and a phase-locked loop circuit. The phase-locked loop circuit will be abbreviated as PPL below.

The excavator generates a reference clock. The frequency of this reference clock is hereinafter referred to as fO. fo is of course a constant.

The first branch divider divides the main reference clock to generate a position control clock.

The up/down counter (hereinafter abbreviated as U/D counter) switches the frequency division ratio N of the first frequency divider.

Of course, N is a natural number.

The control circuit has the following functions. The scanning area is divided in advance into blocks BLi (i = l to K), and a predetermined finite number sequence Mi (i = 1
~K), the i-th block BLi (i=1~
K), for each Mi pulse of the position control clock,
The U/D counter is driven to achieve stepwise switching of the frequency division ratio N over the entire scanning area. That is, if the initial value of the frequency division ratio N is No, then the position control program f.

The frequency of the block is initially -, but the first block BLI
When O counts M1 pulses in this position control block, the control circuit switches the frequency division ratio of the first frequency divider from No to Nt (=No+ΔN) via the U/D counter.

Then, the frequency f of the position control clock.

The wave number is -. When the clock of this new frequency is counted by N□M1 pulses, the frequency division ratio is further changed from N1 to N
Switch to 2. Repeat this n1 times. Subsequently, in the second block BL, switching the frequency division rate for each M2 pulse of the position control block is repeated 02 times.

This process is performed for each block. In the i-th block BLi, switching of the 9 frequency division ratio is performed ni times every Mi pulses of the position control clock.

The PLL circuit includes a phase detection circuit, a low-pass filter, a second frequency divider, and a voltage control excavator. The second frequency divider has a fixed division ratio M.

This PLL circuit generates an image scanning clock whose frequency changes continuously in response to stepwise changes in the frequency of the position control clock.

This image scanning clock generating device will be described below with reference to the drawings.

In FIG. 2, the phase detection circuit 18, the low-pass filter 20, the voltage control excavator 22, and the second frequency divider 24 are
It constitutes an LL circuit.

The reference clock of frequency fo generated from the excavator 10 is divided by the first divider 12 to obtain the frequency f.

This becomes a position control clock of several times, and is input to the control circuit 16° and the phase detection circuit 18 of the PLL circuit.

The phase detection circuit 18 compares the phase of this position control clock and the clock CLA input from the frequency divider 24,
A low-pass filter 20 uses the phase difference as a pulse signal.
Output to. When the information on the phase difference is input to the voltage-controlled excavator 22 via the low-pass filter 20, the excavator 22 outputs a clock having a frequency corresponding to the output voltage of the low-pass filter 20.

The 0-image scanning clock, which serves as the 1-image scanning clock, is frequency-divided by a 5-frequency divider 24, applied to the phase detection circuit 18 as a clock CLA, and compared in phase with the 1-position control clock.

Now, in the PLL circuit, the frequency of the clock emitted from the voltage control excavator 22 does not change when there is no change in the phase difference between the clock CLA whose phase is compared in the phase detection circuit 18 and the position control clock. , such a state will be referred to as the equilibrium state of the PLL circuit.

For example, in the balanced state of a PLL circuit, f for position control.

If the lock frequency is -, then the frequency of the cut clock CLA is also -, so in this state,
Frequency f of the clock emitted from the voltage-controlled excavator 22
x is . In this state, the frequency division ratio of the frequency divider 12 is changed from N to N'
When switching to , the frequency of the position control clock becomes fO・−
Therefore, a phase difference N' occurs between the clock CLA and the clock CLA. Accordingly, the frequency fK of the output clock of the voltage-controlled excavator 22 changes accordingly, but this frequency f
The change in K occurs continuously and changes by the frequency fK.

Therefore, by changing the frequency division ratio N of the 1 frequency divider 12 stepwise, the frequency fK of the image scanning clock can be changed continuously.

Now, the control circuit 16 includes a clock CK for outputting a preset value of the frequency division ratio in the frequency divider 12 from the U/D counter 14, a signal EN for enabling the U/D counter 14 to count, and an up/down mode. A signal U/D is issued to determine the

In the up-down mode, the signal U/D is generated so as to switch from the up mode (or down mode) to the down mode (or up mode) near the extreme value of the scanning speed.

When the clock CK is input, the U/D counter 14 updates the preset value and switches the frequency division ratio of the divider 12.

As mentioned above, the clock IJ is generated by a finite number sequence Mi (i==1) for each block BLi (i=1 to K).
~K). That is, 1Mi and ni are set in advance for each block, and in the i-th block BLi, the control circuit 16 generates a clock CK every time Mi pulses of the position control clock are input. In this block BLi,
This occurs ni times.

The number of blocks, Mi, and ni values are the voltage control excavator 2.
The frequency fg of the image scanning clock generated from 2 is set so as to closely approximate the frequency change 1 caused by the change in scanning speed, for example, equation (1). This is determined experimentally or theoretically depending on design conditions.

Figure 5 shows an example of a stepwise change in the clock f'x due to a change in the ideal image scanning clock fx (curve 4-1) and switching of the division ratio. The numbers 5, 6, 10, and 16 are Ml, M2, and M2, respectively, with the right end of the figure as the scanning start side. Compatible with M3° and M4. As can be seen from the figure, n1 = 6° n2 = 9. n3=
3. n4=5. This figure shows only the right half of the symmetric figure, and M5=10. n5=3.

M6=6, n6=9, M7=5, n
7=6. As you can see from this diagram, block B
Li is an area where a continuous curve of one frequency fK is linearly approximated, and within each block, the width of the step is equal. The clock f'x corresponds to M times the position control clock. Although the clock f'x itself changes stepwise,
Due to the action of the PLL circuit, the frequency of the actual image scanning clock changes continuously and closely approximates one curve 4-1.

FIG. 3 shows an explanatory timing diagram of the apparatus shown in FIG. From top to bottom: synchronization signal, scanning speed f.

1 frequency division ratio N, position control clock frequency - 1 image scanning clock frequency fK. U/D counter 1
Since the up/down mode of No. 4 is switched near the extreme value of the scanning speed, the frequency division ratio N, fo/N, and fk are all symmetrical with respect to the position near the above-mentioned extreme value.

The synchronization signal is the output of the optical sensor shown at 36 in FIG. 4, and the first branch 12 is initialized by this synchronization signal. The synchronization signal is also applied to the control circuit 16.

The signal EN causes the counter operation to be performed with a delay of a predetermined time Ta after receiving the synchronization signal, and after the print area scan is completed,
The counter operation is ended after a delay of Tb time.

With the end of the counter operation.

The division ratio N is fixed to an initial value.

The optical scanning device further has a circuit that generates a recording position instruction signal, and this circuit is initialized by a synchronization signal from the optical sensor 36, counts the position control clock from the branching unit 12, and changes the count value from a certain value. A recording position instruction signal is generated when a different value is reached. This recording position instruction signal and the image scanning clock are sent to an external device, and this external device sends out an image signal in synchronization with the image scanning clock when the recording position instruction signal is input. This image signal is applied to the modulation means to modulate the light beam L, turning on/off a semiconductor laser that generates the light beam, for example, and forming a latent image on the photoreceptor 30.

However, in the above-mentioned optical scanning device, the synchronization signal from the optical sensor 36 varies due to the rotating deflector 32, and the position control clock from the splitter 12 and the clock C from the frequency divider 24
Since the phase with LA is shifted, the phases of the image scanning clock and the recording position instruction signal are no longer aligned, and a part of the image signal may be lost, resulting in a decrease in image quality.

(Objective) An object of the present invention is to provide an optical scanning device that can improve image quality by aligning the phases of an image scanning clock and a recording position instruction signal.

(Structure) The present invention includes a counter that is initialized by a synchronization signal from an optical sensor and counts a position control clock, and a PL for generating an image scanning clock by counting a predetermined value of this counter.
The PLL circuit comprises means for generating a recording position instruction signal in synchronization with either the rising edge or the falling edge of the frequency divider output in the L circuit, and the selecting means for selecting either the rising edge or the falling edge. A recording position instruction signal whose phase is aligned with the generated image scanning clock is generated.

Next, one embodiment of the present invention will be described.

In this embodiment, as shown in FIG.
1. It is composed of a JK flip-flop 42 and a selection circuit 43, and the selection circuit 43 is composed of an inverter 44 and a switch 45.

The counter 41 is initialized (reset) by a synchronization signal from the optical sensor 36 and counts the position control unit clock from the 1 frequency divider 12. When the contents of the flip-flop 42 and the counter 41 reach the first value and the second value, respectively, which approximately correspond to the beginning and end of the printing period (period in which a latent image is formed on the photoreceptor 30) within each scanning period. The output signal of the counter 41 is input to the terminal J, and the clock C is input from the 1 frequency divider 24.
LA is input via the selection circuit 43. switch 45
When the movable contact piece is switched to the rising side fixed terminal U, the clock CLA from the frequency divider 24 is input to the flip-flop 42 as is. Therefore, flip-flop 42
is set at the rising edge of the clock CLA after the contents of the counter 41 reaches the first value, and generates a recording position instruction signal, and after the contents of the counter 41 reaches the second value, the clock CLA is set at the rising edge of the clock CLA. It is reset with ``Tate'' Yuri.

Further, when the movable contact of the switch 45 is switched to the falling side fixed terminal, the clock CLA from the 9 frequency divider 24 is inverted by the inverter 44 and input to the flip-flop 42. Therefore, the flip-flop 42 is reset at the rising edge of the clock CLA after the contents of the counter 41 reaches the first value, and generates a recording position instruction signal, and after the contents of the counter 41 reaches the second value. clock CLA
It is reset at the falling edge of . Therefore, whether the recording position instruction signal is generated at the rising edge of clock CLA or
The switch 45 can be used to select whether the recording device instruction signal is generated at the falling edge of the recording device instruction signal. This recording position instruction signal and the image scanning clock are sent to an external device.

When the recording position instruction signal is input, the external device sends an image signal to the modulation means of this embodiment in synchronization with the image scanning clock, and the modulation means uses the image signal to adjust the light beam L.
Modulate.

(Effects) As described above, according to the present invention, a counter is initialized by a synchronization signal, the counter is caused to count the position control clock, and the frequency divider output of the PLL circuit for image scanning clock generation is determined by the predetermined count. Since the recording position instruction signal can be selected in synchronization with either the rising edge or the falling edge, the phases of the one-image scanning clock and the recording position instruction signal can be aligned, eliminating the loss of part of the image signal and improving the image quality. Quality can be improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a part of an embodiment of the present invention, FIG. 2 is a block diagram showing an example of an image scanning clock generation device in an optical scanning device, and FIG. 3 is a timing diagram of the image scanning clock generation device. 4 is a plan view showing an example of the optical scanning device, and FIG. 5 is a diagram for explaining the optical scanning device. 41...Counter, 42...Flip-flop. V J Shaku

Claims (1)

[Claims] This is an optical scanning device that deflects a light beam with a rotating polygon mirror and scans the surface to be scanned with the light beam without using an fθ lens. A phase-locked loop that is composed of a first frequency divider that generates a control clock, a phase comparator, a low-pass filter, a voltage controlled oscillator, and a second frequency divider, and that generates an image scanning clock using the position control clock. a circuit; a control means for changing the frequency division ratio of the first frequency divider stepwise to continuously change the frequency of the image scanning clock according to the scanning speed of the light beam;
an optical sensor that detects the light beam outside the image scanning area;
In an optical scanning device having means for modulating the light beam by obtaining an image signal in synchronization with the image scanning clock based on a recording position instruction signal, the position control clock is initialized by a synchronization signal from the optical sensor. a counter for counting, a means for generating the recording position instruction signal in synchronization with either a rising edge or a falling edge of the output signal of the second frequency divider by counting a predetermined value of the counter; 1. An optical scanning device comprising: a selection means for selecting either a falling edge or a falling edge.