JPH01181573A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To improve a programming speed by providing a P-type diffused layer region in a drain near a tunnel insulating film. CONSTITUTION:In an EEPROM(electrically erasable and programmable read only memory), programming and erasure are performed by a tunnel phenomenon through a thin tunnel oxide film 5. As a P-type diffused layer 9 is provided in a drain (N-type diffused layer) 3 region near the tunnel oxide film 5, positive holes are supplied to the part under the tunnel oxide film 5 from the P-type diffused layer 9 to form an inversion layer 11 quickly and a voltage drop caused by the spread of a depletion layer can be suppressed. With this constitution, programming and erasure can be performed in a short time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor device, and particularly to the structure and manufacturing method of an EEPROM (electrically erasable and rewritable read-only memory).

(Conventional technology) FIG. 3 shows a cross-sectional structure of a conventional EEFROM.

It has an N-type diffusion layer for a source 2 and a drain 3 in a P-type silicon substrate 1, and has a thin tunnel oxide film 5 on a part of the gate oxide film 4 above the drain 3, and a floating layer on this gate oxide film 4. It has a two-layer gate structure including a polysilicon gate 6 and a control polysilicon gate 7.

FIG. 4 shows the operating principle of this conventional EEFROM during writing (electron extraction).

When the control polysilicon gate 8 is set to the ground potential, the source 2 is set to a potential of 0 or about 5 V, and a voltage of about 10 V is applied to the drain 3, a depletion layer 10 expands in the drain 3, and then P is formed under the tunnel oxide film 5. A type inversion layer 11 is formed, and electrons flow out from the floating polysilicon gate 6 to the drain 3 due to the tunnel effect.

(Problem to be Solved by the Invention) In this conventional EEPROM structure, when a high voltage (more than 10 volts) is applied to the drain 3 during writing (electron extraction), holes are generated near the tunnel oxide film 5. No supply source exists. Therefore, electron-hole pairs are generated in the depletion layer 10 due to the gushing of holes from the drain (N-type diffusion layer) 3 or the injection of tunnel current from the floating gate 6, which causes the inversion to occur directly below the tunnel oxide film 5. Until the layer 11 is formed, the depletion layer 10 continues to extend on the surface of the drain 3, and in order to cause a voltage drop in the depletion layer 10, a sufficient voltage is applied to the tunnel oxide film 5 to extract electrons from the floating gate 6. is not applied. Therefore, there is a drawback that it takes time to form the inversion layer 11 and the programming time becomes long.

Therefore, an object of the present invention is to increase the programming speed of the EEFROM by providing a hole supply source near the tunnel oxide film.

[Structure of the invention]

(Means for Solving the Problems) In the present invention, an N-type diffusion layer serving as a source and a drain is arranged in the surface layer of a P-type semiconductor substrate with a channel region sandwiched therebetween, and the surface of the channel region and the source and drain A floating gate is disposed on a portion of the surface of the drain via an insulating film, a tunnel insulating film thinner than the surroundings is disposed on a portion of the gate insulating film on the drain surface, and a control gate is disposed on the surface of the floating gate with an insulating film interposed therebetween. The present invention provides a semiconductor device characterized in that a P-type diffusion layer region is provided in the drain near the tunnel insulating film.

The present invention also provides a source within the surface layer of a P-type semiconductor substrate.

A step of forming an N-type diffusion layer that will become a drain across a channel region, a step of forming a P-type diffusion layer region in the drain near a region where a tunnel insulating film is to be formed, and a step of forming a gate insulating layer on the surface of the semiconductor substrate. forming a tunnel insulating film, and removing a region of the gate insulating film where a tunnel insulating film is to be formed to form a tunnel insulating film thinner than the surrounding area in this region, and forming a layer of a substance to become a floating gate on the surface of the gate insulating film. a step of forming an insulating film on the surface of the layer of material that will become the floating gate; a step of forming a layer of material that will become the control gate on the surface of the insulating film; a layer of the material that will become the floating gate; forming a two-layer gate consisting of a floating gate and a control gate by removing an insulating film and a layer of material that will serve as a control gate, leaving only regions above the channel region and a portion of the source/drain. A method for manufacturing the device is provided.

(Function) The EEFROM according to the present invention is a floating gate type EEFROM with a two-layer structure.
This is an EFROM, and writing and erasing is performed by tunneling through a thin tunnel oxide film, but since a P-type diffusion layer is provided near the tunnel oxide film in the drain (N-type diffusion layer) region, this P-type Holes are supplied from the diffusion layer to the bottom of the tunnel oxide film, quickly forming an inversion layer, and suppressing the voltage drop due to the expansion of the depletion layer. the result,
Writing and erasing can be done in a short time.

(Example) Examples will be explained below.

FIG. 1 shows the structure of an embodiment of an EEPROM according to the present invention.

In this embodiment, a source 2 is provided in the surface layer of a P-type semiconductor substrate 1;
An N-type diffusion layer that will become the drain 3 is placed across the channel region, and a floating gate 6 is placed over the channel region and part of the source 2 and drain 3 with a gate insulating film 4 interposed therebetween. In a part of the gate insulating film 4, there is a tunnel oxide film 5 that is thick enough to cause a tunnel effect and thinner than the surrounding area, and a control gate 8 is placed on the floating gate 6 with an insulating film 7 interposed therebetween. It has a structure in which a P-type diffusion layer 9 is arranged in a part of the drain 9 near the drain 9.

Next, an embodiment of the manufacturing method according to the present invention will be described according to 21st ffl (a) to (d).

First, N-type diffusion layers and P-type diffusion layers 9 of the source 2 and drain 3 are formed at specified positions on a P-type silicon substrate 1 by ion implantation using a photoresist as a mask (FIG. 2(a)).

Next, after removing the resist mask, a thermal oxide film 4a of about 400A is formed on the entire surface of the substrate 1, and the surface is covered with a photoresist patterned in the area where the tunnel oxide film is to be formed, and this is used as a mask. The tunnel oxide film formation P constant region of the thermal oxide film 4a is removed using NH4F or the like.

Thereafter, thermal oxidation is performed to form a tunnel oxide film 5 of about 100 Å (FIG. 4(b)). Next, after depositing a first polysilicon layer 6a on the thermal oxide film 4a, an insulating film 7a such as a polysilicon oxide film is formed thereon, and a second polysilicon layer 8a is deposited thereon (see FIG. (C)). Thereafter, using the photoresist patterned in the region where the gate is to be formed as a mask, the second polysilicon layer 8 a s insulating film 7 is formed.
aS The first polysilicon layer 6a is sequentially removed to form a two-layer gate (FIG. 4(d)).

In this structure, since the P-type diffusion region 9 is provided in the drain (N'42 diffusion layer) 3 near the tunnel oxide film 5, the control gate 8 is set to the ground potential and a programming voltage is applied to the drain 3. floating gate 6 to drain 3
During the operation of extracting electrons, holes for forming the P-type inversion layer 11 formed under the tunnel oxide film 5 are supplied from the P-type diffusion region 9, thereby speeding up the formation of the inversion layer 11 and withdrawing electrons. It can shorten the time.

〔Effect of the invention〕

As explained above, according to the present invention, a diffusion region that supplies holes for forming an inversion layer is provided in the drain near the tunnel oxide film, so that holes are supplied from this diffusion layer during programming to form an inversion layer. The formation is promoted, and the effect is that the electron extraction time, that is, the programming time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the structure of an embodiment of an EEPROM according to the present invention, FIG. 2 is a cross-sectional view showing an embodiment of the EEFROM manufacturing method according to the present invention in the order of steps, and FIG. 3 is a conventional EEFROM. FIG. 4 is a cross-sectional view showing the structure of FIG. DESCRIPTION OF SYMBOLS 1... P-type silicon substrate, 2... Source (N-type diffusion layer), 3... Drain (N-type diffusion layer), 4... Gate oxide film, 5... Tunnel oxide film, 6 ...Floating gate, 7...Insulating film, 8...Control gate, 9...P
Type diffusion layer, 10... Depletion layer, 11... Inversion layer. Applicant's agent Sato - Yuma 1 Figure Map 3 Figure Map 4 Figure 3F:) 2 Figure

Claims (1)

[Claims] 1. N in the surface layer of the P-type semiconductor substrate to serve as the source and drain
A type diffusion layer is disposed across a channel region, a floating gate is disposed on a surface of the channel region and a portion of the source and drain via an insulating film, and a floating gate is disposed on a portion of the gate insulating film on the surface of the drain. There is a tunnel insulating film thinner than the surroundings, and a control gate is arranged on the surface of the floating gate via the insulating film, characterized in that a P-type diffusion layer region is provided in the drain near the tunnel insulating film. semiconductor device. 2. N that becomes the source and drain in the surface layer of the P-type semiconductor substrate
forming a type diffusion layer across a channel region; forming a P-type diffusion layer region in the drain near a region where a tunnel insulating film is to be formed; forming a gate insulating film on the surface of the semiconductor substrate; a step of removing a region of the gate insulating film where a tunnel insulating film is to be formed and forming a tunnel insulating film thinner than the surrounding area in this region; a step of forming a layer of a substance to become a floating gate on the surface of the gate insulating film; a step of forming an insulating film on the surface of the layer of material that will become the floating gate; a step of forming a layer of material that will become the control gate on the surface of the insulating film; and a step of forming the layer of material that will become the floating gate, the insulating film, and the control gate. A method for manufacturing a semiconductor device, comprising the step of removing a layer of material that will serve as a gate, leaving only a region above the channel region and a portion above the source/drain to form a two-layer gate consisting of a floating gate and a control gate. .