JPH01179507A - Gain stabilizing differential amplifier - Google Patents
Gain stabilizing differential amplifierInfo
- Publication number
- JPH01179507A JPH01179507A JP63003405A JP340588A JPH01179507A JP H01179507 A JPH01179507 A JP H01179507A JP 63003405 A JP63003405 A JP 63003405A JP 340588 A JP340588 A JP 340588A JP H01179507 A JPH01179507 A JP H01179507A
- Authority
- JP
- Japan
- Prior art keywords
- differential amplifier
- gain
- current source
- current
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000000087 stabilizing effect Effects 0.000 title claims abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 3
- 230000003321 amplification Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/4508—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using bipolar transistors as the active amplifying circuit
- H03F3/45085—Long tailed pairs
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45244—Indexing scheme relating to differential amplifiers the differential amplifier contains one or more explicit bias circuits, e.g. to bias the tail current sources, to bias the load transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
〔1既 要〕
利得安定化差動増幅器に関し、
高利得で利得の安定な差動増幅器の提供を目的とし、
同じ値の負荷抵抗を夫々コレクタ側に有し、夫々のエミ
ッタは接続されて第1の電流源に接続され差動対を構成
している第1.第2のトランジスタの、夫々のベースを
入力とし、夫々のコレクタを出力とする差動増幅器にお
いて、
コレクタ側に第1の抵抗を有し、且つエミッタ側は第2
の抵抗を介して第2の電流源に接続されている第3のト
ランジスタ及び、エミッタ側は第3の抵抗を介して該第
2の電流源に接続されている第4のトランジスタを設け
、且つ該第1の電流源と該第2の電流源とは電流を制御
する制御線で接続してカレントミラー回路とし、
且つ該第3.第4のトランジスタ夫々のエミッタを入力
とし該制御線を出力とする差動アンプを設けた構成とす
る。[Detailed Description of the Invention] [1 Required] Regarding a gain-stabilized differential amplifier, the object of the present invention is to provide a differential amplifier with a high gain and a stable gain. The emitters of the first . In a differential amplifier in which the respective bases of the second transistors are inputs and the respective collectors are outputs, the collector side has a first resistor, and the emitter side has a second resistor.
a third transistor connected to the second current source via a resistor; and a fourth transistor whose emitter side is connected to the second current source via a third resistor; The first current source and the second current source are connected by a control line for controlling current to form a current mirror circuit, and the third. The configuration includes a differential amplifier whose input is the emitter of each of the fourth transistors and whose output is the control line.
本発明は、電子機器1通信機器等に使用されるIC化に
適した利得安定化差動増幅器に関する。The present invention relates to a gain stabilizing differential amplifier suitable for integration into an IC for use in electronic equipment, communication equipment, and the like.
差動増幅器をIC化すると小形になる為利得が温度に敏
感になり又トランジスタ各部の特性のばらつきで利得に
ばらつきが生ずる。When a differential amplifier is made into an IC, the size becomes smaller, so the gain becomes sensitive to temperature, and variations in the characteristics of each part of the transistor cause variations in the gain.
この為利13の安定な差動増幅器とする必要があるが、
高利得であることが望ましい。For this reason, it is necessary to create a stable differential amplifier with a profit margin of 13.
A high gain is desirable.
以下従来例を図を用いて説明する。 A conventional example will be explained below using figures.
第3図は従来例の差動増幅器の回路図である。FIG. 3 is a circuit diagram of a conventional differential amplifier.
図中Q1、Q2.Q7.Q8はNPN)ランジスタ、P
CI’ 、RC2°は値の等しい負荷抵抗、Re1、R
’e2は値の等しい帰還抵抗、R6−R8は抵抗を示し
、差動増幅器としては、トランジスタQ1、Q2のベー
スを入力としコレクタを出力としている。In the figure, Q1, Q2. Q7. Q8 is NPN) transistor, P
CI', RC2° are load resistances with equal values, Re1, R
'e2 is a feedback resistor of equal value, R6-R8 are resistors, and as a differential amplifier, the bases of transistors Q1 and Q2 are input, and the collector is output.
尚トランジスタQ7.抵抗R7で電流源を構成し、又抵
抗R6,トランジスタQ7と同特性のトランジスタQB
、抵抗7と同一値の抵抗R8を直列にして電源電圧間に
挿入し、トランジスタQ8と07のベースを電流制御線
で接続し、トランジスタQ8に流れる電流と電流源の電
流I0とが等しいカレントミラー回路を作り、電流源の
電流■。を温度変化に対して安定にしている。Furthermore, transistor Q7. The resistor R7 constitutes a current source, and the resistor R6 and the transistor QB having the same characteristics as the transistor Q7
, a resistor R8 with the same value as resistor 7 is inserted in series between the power supply voltages, and the bases of transistors Q8 and 07 are connected by a current control line to create a current mirror in which the current flowing through transistor Q8 is equal to the current I0 of the current source. Create a circuit and calculate the current of the current source ■. is stable against temperature changes.
この差動増幅器としては、エミッタ側に帰還抵抗R13
1,Ra2を設は負帰還をかけ利得の安定化を計ってい
る。This differential amplifier has a feedback resistor R13 on the emitter side.
1, Ra2 is set to apply negative feedback to stabilize the gain.
しかしながら、負帰還をかけている為、利得変動は小さ
くなるも利得が低下する問題点がある。However, since negative feedback is applied, there is a problem that the gain decreases even though the gain fluctuation is reduced.
本発明は、高利得で利得の安定な差動増幅器の提供を目
的としている。The present invention aims to provide a differential amplifier with high gain and stable gain.
第1図は本発明の原理回路図である。 FIG. 1 is a circuit diagram of the principle of the present invention.
第1図に示す如く、同じ値の負荷抵抗RC1。As shown in FIG. 1, the load resistance RC1 has the same value.
RC2を夫々コレクタ側に有し、夫々のエミッタはt2
¥続されて第1の電流源1に接続され差動対を構成して
いる第1.第2のトランジスタQ1、Q2の、夫々のベ
ースを入力とし、夫々のコレクタを出力とする差動増幅
器において、
コレクタ側に第1の抵抗R3を有し、且つエミッタ側は
第2の抵抗R2を介して第2の電流源2に接続されてい
る第3のトランジスタQ3及び、エミッタ側は第3の抵
抗R1を介して該第2の電流源2に接続されている第4
のトランジスタQ4を設ける。RC2 on the collector side, and each emitter has t2
The first current source 1 is connected to the first current source 1 to form a differential pair. In a differential amplifier in which the respective bases of the second transistors Q1 and Q2 are used as inputs, and the respective collectors are used as outputs, a first resistor R3 is provided on the collector side, and a second resistor R2 is provided on the emitter side. A third transistor Q3 is connected to the second current source 2 through a third transistor Q3, and a fourth transistor Q3 whose emitter side is connected to the second current source 2 through a third resistor R1.
A transistor Q4 is provided.
そして、該第1の電流源1と該第2の電流源2とは電流
を制御する制御線4で接続してカレントミラー回路とす
る。The first current source 1 and the second current source 2 are connected by a control line 4 for controlling current to form a current mirror circuit.
尚且つ、該第3.第4のトランジスタQ3.Q4夫々の
エミッタを入力とし該制御線4を出力とする差動アンプ
3を設けた構成とする。Furthermore, the third. Fourth transistor Q3. The configuration is such that a differential amplifier 3 is provided which receives the emitter of each Q4 as an input and uses the control line 4 as an output.
差動対の利得Gvは次式(1)で与えられる。 The gain Gv of the differential pair is given by the following equation (1).
GV=(α・RC/h)(Is/2)□ (RC/h)
(Io/2) ” ’ (1)但し、RCはコレクタ
抵抗(負荷抵抗)、パラメータh=に−T/q、、には
ボルツマン定数、qは電子の電荷、Tは絶対温度、Io
は電流源の電流、αは電流増倍率で通常は略1である。GV = (α・RC/h) (Is/2)□ (RC/h)
(Io/2) '' (1) However, RC is the collector resistance (load resistance), the parameter h = -T/q, , is the Boltzmann constant, q is the electron charge, T is the absolute temperature, Io
is the current of the current source, and α is the current multiplication factor, which is usually approximately 1.
電流源の電流■。を次式(2)で表すようにすれば、(
1)式は(3)式で表される。Current source current■. If expressed by the following equation (2), (
Equation 1) is expressed by equation (3).
■。=に−h/RI・・・ (2)
Gv=(RC/h) X ((Ilh)/(2・RI)
) =(K −RC)/(2・r?I) ・・・
(3)
(3)式では利得は抵抗比で表されるので安定となる。■. = ni-h/RI... (2) Gv=(RC/h) X ((Ilh)/(2・RI)
) = (K - RC) / (2・r?I) ...
(3) In equation (3), the gain is expressed by the resistance ratio, so it is stable.
つま、す、(2)式を満足する電流源を設ければよいこ
とになる。In short, it is sufficient to provide a current source that satisfies equation (2).
第1図で、差動アンプ3の利得を無限大とすると、差動
アンプ3.電流源2.電流源2の電流を制御する制御線
4.トランジスタQ3.Q4よりなるループは、第1図
のa点とb点が同電位にあると安定する。In FIG. 1, if the gain of the differential amplifier 3 is infinite, then the differential amplifier 3. Current source 2. A control line 4 for controlling the current of the current source 2. Transistor Q3. The loop formed by Q4 becomes stable when points a and b in FIG. 1 are at the same potential.
従って、b/lz・R2/R1・・・・(4)となり、
12 ’ R3+ V bsl”V ba4 となる。Therefore, b/lz・R2/R1...(4),
12' R3+ V bsl"V ba4.
但し 、V baff+ baaはトランジスタQ3
.Q4のペースエミッタ電圧、■、、 Izはトランジ
スタQ4.Q3を流れる電流である。However, V baff+ baa is transistor Q3
.. The pace emitter voltage of Q4, ■, Iz is the voltage of transistor Q4. This is the current flowing through Q3.
よって、電流I2は次式(5)となる。Therefore, the current I2 is expressed by the following equation (5).
h□(V baa −V w:+)/R3= ((h−
fnl+/I s+)−(h−j2nlz/I sz)
) /R3・(h/lン3) X ji! nR2/
R1・’・(5)
但し、I Sl+ 132はトランジスタQ4.Q3の
逆飽和電流である。h□(V baa −V w:+)/R3= ((h−
fnl+/I s+)-(h-j2nlz/I sz)
) /R3・(h/ln3) X ji! nR2/
R1·'·(5) However, I Sl+ 132 is the transistor Q4. This is the reverse saturation current of Q3.
又電流源1と電流源2とはカレントミラー回路となって
いるので、
1o−1++Ig=(h/R3) ((R2/R1)
+l ) X j2nR2/R1=に(h/R3
)・・・・(6)となる。Also, since current source 1 and current source 2 are a current mirror circuit, 1o-1++Ig=(h/R3) ((R2/R1)
+l) X j2nR2/R1=(h/R3
)...(6).
(6)式は(2)式を満足するので、このトランジスタ
Q3.Q4.差動アンプ3.電流源2を含む回路を用い
れば利得の安定な差動増幅器が得られることになる。Since equation (6) satisfies equation (2), this transistor Q3. Q4. Differential amplifier 3. If a circuit including the current source 2 is used, a differential amplifier with stable gain can be obtained.
この場合の電流I0を電流源の電流とする差動対の利得
Anは(1)式を法に次式(7)の如く、抵抗比で定ま
り利得は安定する。In this case, the gain An of the differential pair in which the current I0 is the current of the current source is determined by the resistance ratio as shown in the following equation (7) based on the equation (1), and the gain is stable.
A n =(RC/h)(Io/2)・(K/2)(R
C/R3) ・・・(7)但し、RC=RC1=RC
2である。A n =(RC/h)(Io/2)・(K/2)(R
C/R3) ... (7) However, RC=RC1=RC
It is 2.
このトランジスタQ1、Q2を用いた差動対は負帰還の
帰還抵抗を用いず利得は安定であるので、この差動対を
用いた差動増幅器は高利得にすることが出来る。Since this differential pair using transistors Q1 and Q2 does not use a feedback resistor for negative feedback and has a stable gain, a differential amplifier using this differential pair can have a high gain.
以下本発明の1実施例に付き図に従って説明する。 An embodiment of the present invention will be described below with reference to the accompanying drawings.
第2図は本発明の、実施例の回路図である。FIG. 2 is a circuit diagram of an embodiment of the present invention.
動アンプ、Ql−Ql2.Ql4.Ql6.Q18〜Q
20.Q22.Q23はNPN )ランジスタ、Ql3
.Ql5.Ql7.Q21はPNP )ランジスタ、C
はコンデンサ、PC1、RC2は同じ値の負荷抵抗、R
1−R11は抵抗を示し、R4= R5である。dynamic amplifier, Ql-Ql2. Ql4. Ql6. Q18~Q
20. Q22. Q23 is NPN) transistor, Ql3
.. Ql5. Ql7. Q21 is PNP) transistor, C
is a capacitor, PC1 and RC2 are load resistances of the same value, and R
1-R11 indicates resistance, and R4=R5.
l・ランジスタQ1、Q2の差動対及び電流源1を用い
た差動増幅器及び、トランジスタQ3.Q4及び電流源
2を用いた回路は第1図と同じで動作も同じであるので
説明は省略するが、電流源1のトランジスタQ5.抵抗
R5は夫々、電流源2のトランジスタQ6と同特性で抵
抗R4と同じ値であり、電流源1と電流源2はカレンI
・ミラー回路となっている。A differential amplifier using a differential pair of transistors Q1 and Q2 and a current source 1, and a transistor Q3. The circuit using transistor Q4 and current source 2 is the same as in FIG. 1, and the operation is the same, so the explanation will be omitted. Each resistor R5 has the same characteristics as the transistor Q6 of current source 2 and the same value as resistor R4, and current source 1 and current source 2 have the same characteristics as transistor Q6 of current source 2.
・It is a mirror circuit.
差動アンプ3は利得の大きいアンプで、トランジスタQ
13.Q14、Ql5.Ql6、Ql7゜Ql8、Q2
1.Q22は夫々ダーリントン接続となっており電流増
幅率を非常に大きくしてあり、又トランジスタQ15〜
Q18を用いて差動対を構成し利得を更に大きくしてい
る。Differential amplifier 3 is a high-gain amplifier, and transistor Q
13. Q14, Ql5. Ql6, Ql7゜Ql8, Q2
1. Q22 are each Darlington connected to have a very large current amplification factor, and transistors Q15 to
A differential pair is constructed using Q18 to further increase the gain.
この差動アンプ3は、トランジスタQ7.Q8、Q10
.Qllよりなる同じ回路のトランジスタQ7.Q10
のベースを入力とし、トランジスタQB、Qllのエミ
ッタより、前記のダーリントン接続の差動対に入力し、
大きく増幅されて、トランジスタQ20のコレクタより
制御線4に対して出力するようになっている。This differential amplifier 3 includes transistors Q7. Q8, Q10
.. Transistor Q7. of the same circuit consisting of Qll. Q10
The base of is input, and the emitters of transistors QB and Qll are inputted to the Darlington-connected differential pair,
The signal is greatly amplified and output from the collector of the transistor Q20 to the control line 4.
そこで、差動アンプ3は、第2図の■、■点の電位差を
検出し、この電位差がOになるように動トランジスタQ
6のコレクタ電流を増加し、抵抗R3による電圧降下を
増加し、■の電位を下げ、逆に■より■の電位が低けれ
ば、トランジスタQ6のコレクタ電流を減じ、■の電位
を高くするように働く。Therefore, the differential amplifier 3 detects the potential difference between points ■ and ■ in FIG.
Increase the collector current of transistor Q6, increase the voltage drop through resistor R3, and lower the potential of work.
このようにして■と0点の電位差が略Oの所で回路は安
定する。In this way, the circuit becomes stable when the potential difference between the point ■ and the zero point is approximately O.
コンデンサCは上記の動作を安定にさせる為のものであ
る。Capacitor C is used to stabilize the above operation.
■■の2点の電位が等しければ、先に説明した(4)式
、 (5)式が成立し、トランジスタQ6とQ5のコレ
クタ電流は(2)式と同等となり、トランジスタQ1、
Q2.抵抗RC1、Re2及び電流源1で構成されてい
る差動増幅器の利得は(7)式に示す通りになる。If the potentials at the two points of
Q2. The gain of the differential amplifier composed of resistors RC1, Re2 and current source 1 is as shown in equation (7).
即ち、利得は抵抗比で定められ、電源変動、温度変動、
トランジスタの特性のばらつきに無関係となるので、負
帰還をかけなくてもよく高利得とすることが出来る。In other words, the gain is determined by the resistance ratio, and is subject to power supply fluctuations, temperature fluctuations,
Since it is independent of variations in transistor characteristics, a high gain can be achieved without the need for negative feedback.
従来例の回路を4段用い利得を40dBとし、周囲温度
を0度〜85度迄変化すると、40dB±2dBの利得
変動があったが、本発明の回路を3段用い利得を40d
Bとし、周囲温度を上記と同じく変動したら、40dB
±0.05dB程度の変動となった。Using a conventional circuit with four stages and a gain of 40 dB, when the ambient temperature was changed from 0 degrees to 85 degrees, there was a gain variation of 40 dB ± 2 dB, but using a three-stage circuit of the present invention and a gain of 40 dB.
B, and if the ambient temperature changes as above, it will be 40 dB.
The fluctuation was about ±0.05 dB.
変動幅を従来の2dBにすれば、更に高利得とすること
が出来る。If the fluctuation width is reduced to 2 dB, which is the conventional value, an even higher gain can be achieved.
以上詳細に説明せる如く本発明によれば、高利得で利得
が安定な差動増幅器が得られる効果がある。As explained in detail above, according to the present invention, a differential amplifier with high gain and stable gain can be obtained.
第1図は本発明の原理回路図、
第2図は本発明の実施例の回路図、
第3図は従来例の差動増幅器の回路図である。
図において、
1.2,4.5は電流源、
3は差動アンプ、
6は電流源制御回路、
Ql−Q23はトランジスタ、
R1−R11は抵抗、
RC1、Re2.RCI’ 、Re2’ は負荷抵抗、
Rat、Re2は帰還抵抗、
Cはコンデンサを示す。FIG. 1 is a circuit diagram of the principle of the present invention, FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIG. 3 is a circuit diagram of a conventional differential amplifier. In the figure, 1.2, 4.5 are current sources, 3 is a differential amplifier, 6 is a current source control circuit, Ql-Q23 are transistors, R1-R11 are resistors, RC1, Re2. RCI' and Re2' are load resistances,
Rat and Re2 are feedback resistors, and C is a capacitor.
Claims (1)
に有し、夫々のエミッタは接続されて第1の電流源(1
)に接続され差動対を構成している第1、第2のトラン
ジスタ(Q1、Q2)の、夫々のベースを入力とし、夫
々のコレクタを出力とする差動増幅器において、 コレクタ側に第1の抵抗(R3)を有し、且つエミッタ
側は第2の抵抗(R2)を介して第2の電流源(2)に
接続されている第3のトランジスタ(Q3)及び、エミ
ッタ側は第3の抵抗(R1)を介して該第2の電流源(
2)に接続されている第4のトランジスタ(Q4)を設
け、且つ該第1の電流源(1)と該第2の電流源(2)
とは電流を制御する制御線(4)で接続してカレントミ
ラー回路とし、 且つ該第3、第4のトランジスタ(Q3、Q4)夫々の
エミッタを入力とし該制御線(4)を出力とする差動ア
ンプ(3)を設けたことを特徴とする利得安定化差動増
幅器。[Claims] Load resistors (RC1, RC2) of the same value are respectively provided on the collector side, and the emitters of each are connected to each other to generate a first current source (1).
), the bases of the first and second transistors (Q1, Q2) forming a differential pair are input, and the collectors thereof are output. a third transistor (Q3), which has a resistor (R3) of The second current source (
2) a fourth transistor (Q4) connected to the first current source (1) and the second current source (2);
are connected by a control line (4) that controls the current to form a current mirror circuit, and the emitters of the third and fourth transistors (Q3, Q4) are input, and the control line (4) is output. A gain stabilizing differential amplifier characterized in that a differential amplifier (3) is provided.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63003405A JPH07101825B2 (en) | 1988-01-11 | 1988-01-11 | Gain-stabilized differential amplifier |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63003405A JPH07101825B2 (en) | 1988-01-11 | 1988-01-11 | Gain-stabilized differential amplifier |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01179507A true JPH01179507A (en) | 1989-07-17 |
JPH07101825B2 JPH07101825B2 (en) | 1995-11-01 |
Family
ID=11556474
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63003405A Expired - Fee Related JPH07101825B2 (en) | 1988-01-11 | 1988-01-11 | Gain-stabilized differential amplifier |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH07101825B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7746168B2 (en) | 2006-01-04 | 2010-06-29 | Fujitsu Semiconductor Limited | Bias circuit |
EP2339747A1 (en) * | 2009-12-28 | 2011-06-29 | STmicroelectronics SA | Bias circuit for differential amplifier |
-
1988
- 1988-01-11 JP JP63003405A patent/JPH07101825B2/en not_active Expired - Fee Related
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7746168B2 (en) | 2006-01-04 | 2010-06-29 | Fujitsu Semiconductor Limited | Bias circuit |
EP2339747A1 (en) * | 2009-12-28 | 2011-06-29 | STmicroelectronics SA | Bias circuit for differential amplifier |
FR2954866A1 (en) * | 2009-12-28 | 2011-07-01 | St Microelectronics Sa | POLARIZATION CIRCUIT FOR DIFFERENTIAL AMPLIFIER |
US8212616B2 (en) | 2009-12-28 | 2012-07-03 | Stmicroelectronics Sa | Biasing circuit for differential amplifier |
Also Published As
Publication number | Publication date |
---|---|
JPH07101825B2 (en) | 1995-11-01 |
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Legal Events
Date | Code | Title | Description |
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LAPS | Cancellation because of no payment of annual fees |