JPH01179435U - - Google Patents
Info
- Publication number
- JPH01179435U JPH01179435U JP7651188U JP7651188U JPH01179435U JP H01179435 U JPH01179435 U JP H01179435U JP 7651188 U JP7651188 U JP 7651188U JP 7651188 U JP7651188 U JP 7651188U JP H01179435 U JPH01179435 U JP H01179435U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- printed wiring
- integrated circuit
- circuit device
- recess
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 3
- 239000002131 composite material Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Die Bonding (AREA)
Description
第1図は本考案の一実施例を示す複合集積回路
装置の半導体チツプを含めたプリント配線基板の
部分断面図である。 1……プリント配線基板、2……アルミナセラ
ミツク板、3……半導体チツプ、4……抜け穴、
5……配線、6……金属細線、7……窪み部。
装置の半導体チツプを含めたプリント配線基板の
部分断面図である。 1……プリント配線基板、2……アルミナセラ
ミツク板、3……半導体チツプ、4……抜け穴、
5……配線、6……金属細線、7……窪み部。
Claims (1)
- 半導体素子が形成された半導体チツプをプリン
ト配線基板に搭載してなる複合集積回路装置にお
いて、一表面に抜け穴を有する窪みが形成された
前記プリント配線基板と、前記窪みに埋設された
前記半導体チツプと同程度の大きさのアルミナセ
ラミツク板と、前記アルミナセラミツク板に搭載
された前記半導体チツプとを備えることを特徴と
する複合集積回路装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7651188U JPH01179435U (ja) | 1988-06-08 | 1988-06-08 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7651188U JPH01179435U (ja) | 1988-06-08 | 1988-06-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01179435U true JPH01179435U (ja) | 1989-12-22 |
Family
ID=31301534
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7651188U Pending JPH01179435U (ja) | 1988-06-08 | 1988-06-08 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01179435U (ja) |
-
1988
- 1988-06-08 JP JP7651188U patent/JPH01179435U/ja active Pending