JPH0448624U - - Google Patents

Info

Publication number
JPH0448624U
JPH0448624U JP1990090782U JP9078290U JPH0448624U JP H0448624 U JPH0448624 U JP H0448624U JP 1990090782 U JP1990090782 U JP 1990090782U JP 9078290 U JP9078290 U JP 9078290U JP H0448624 U JPH0448624 U JP H0448624U
Authority
JP
Japan
Prior art keywords
semiconductor element
wiring board
conductor pattern
recess
ceramic substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1990090782U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990090782U priority Critical patent/JPH0448624U/ja
Publication of JPH0448624U publication Critical patent/JPH0448624U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Die Bonding (AREA)

Description

【図面の簡単な説明】
図は本考案の一実施例を示し、第1図は配線基
板の平面図、第2図はその断面図、第3図は半導
体素子の取付け状態を示す断面図である。 1……セラミツク基板、2……導体パターン、
2a……凹部、3……半導体素子、4……ハンダ
材。

Claims (1)

  1. 【実用新案登録請求の範囲】 セラミツク基板上に取着した導体パターン上に
    、半導体素子を実装した配線基板において、 該導体パターン上に、該半導体素子と略同じ平
    面形状を持ち該半導体素子を挿入可能な凹部が設
    けられ、該凹部内で該半導体素子がハンダ付けさ
    れていることを特徴とする配線基板。
JP1990090782U 1990-08-29 1990-08-29 Pending JPH0448624U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990090782U JPH0448624U (ja) 1990-08-29 1990-08-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990090782U JPH0448624U (ja) 1990-08-29 1990-08-29

Publications (1)

Publication Number Publication Date
JPH0448624U true JPH0448624U (ja) 1992-04-24

Family

ID=31825804

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990090782U Pending JPH0448624U (ja) 1990-08-29 1990-08-29

Country Status (1)

Country Link
JP (1) JPH0448624U (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009094293A (ja) * 2007-10-09 2009-04-30 Toyota Motor Corp 半導体装置
JP2014053384A (ja) * 2012-09-05 2014-03-20 Toshiba Corp 半導体装置およびその製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009094293A (ja) * 2007-10-09 2009-04-30 Toyota Motor Corp 半導体装置
JP2014053384A (ja) * 2012-09-05 2014-03-20 Toshiba Corp 半導体装置およびその製造方法

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