JPH01177665A - Changeover control circuit for data transfer - Google Patents

Abstract

PURPOSE:To cause a data transfer to be high-speed and high-efficient by arbitrarily switching a transferring quantity to 1-byte width or 2-byte width according to a data capacity, and executing a control so as to load status information on the remaining transmission line of the 1-byte width at the time of the transfer of the 1-byte width. CONSTITUTION:A transfer information control circuit 8 executes the control in switching whether transfer data contents is data information or the status information by information given from a data transferring quantity deciding circuit 4 and a transferring direction control circuit 3 on the transmission line of the 2-byte width sent through an external interface bus 9 to a slave station. Namely, the control is executed so as to arbitrarily switch the transferring quantity to the 1-byte width or 2-byte width according to the data capacity and to load the status information on the remaining transmission line of the 1-byte width at the time of the transfer of the 1-byte width. Thus, a transferring time can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to the amount of data transferred during data transfer, and particularly to a circuit that switches and controls the amount of transfer depending on data content.

(Prior art) Conventionally, in this type of data transfer method, the amount of data transferred is 1
It was fixed to a byte width or a 2-byte width. Additionally, a dedicated transmission line was required to transfer status information.

(Problems to be addressed by the invention) In the conventional data transfer method described above, the amount of data transferred is fixed. Therefore, if a transmission line with a small transfer capacity is used and a large amount of data is transferred, the transfer time will be long, and when the entire transmission line with a large transfer capacity is used, even if the amount of data transferred is small, the transfer time will be longer. However, the disadvantage is that time is wasted.

Furthermore, when exchanging status information, there is a drawback that an entire dedicated transmission path is required.

An object of the present invention is to arbitrarily switch the transfer amount between 1-byte width and 2-byte width according to the data capacity, and when transferring 1-byte width, status information can be placed on the remaining 1-byte width transmission path. It is an object of the present invention to provide a data transfer switching control circuit configured to eliminate the above-mentioned drawbacks and effectively shorten the transfer time by controlling the data transfer as described above.

(Means for Solving All Problems) The data transfer switching control circuit according to the present invention includes an internal bus control circuit and a data transfer amount determining circuit.

A transfer direction control circuit, a status information register circuit,
This configuration includes a transfer information control circuit.

The internal bus control circuit controls the data transfer width of the external interface bus that connects the master station and slave stations, which is composed of a 2-byte wide bidirectional data bus and a coil bus consisting of multiple bits. A byte width instruction that specifies a 1-byte width or a 2-byte width for ', a transfer direction instruction that specifies the direction of data transfer on the external interface bus from the master station to the slave station, or vice versa, and data on the external interface bus. When the transfer byte width is 1 byte wide, this is used to send a status information sending instruction to send the status 6H1l- onto the remaining 1 byte wide external interface bus.

The data transfer amount determining circuit is for holding information on determining the data transfer byte width in accordance with a transfer instruction from the internal bus control circuit.

The transfer direction control circuit is designed to recognize all data transfer direction determination information in accordance with the transfer direction instruction from the internal bus control circuit.

The status information register circuit is for temporarily storing status information.

The transfer information control circuit displays the entire data transfer direction in the transmission direction by the transfer direction control circuit under the condition that the data transfer amount determining circuit indicates a 1-byte width transfer, and also controls the internal bus control circuit. If a status information sending instruction is sent from the status information register circuit, the status information sending instruction is sent to the remaining 9 bytes of the external interface bus, or the transfer direction control circuit changes the transfer direction to the receiving direction. If the data transfer direction is displayed, is this an instruction to accept the status information on the RWE interface bus into the status information register circuit? It is for sending out.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a data transfer switching control circuit according to the present invention.

In FIG. 1, 1 is an internal bus, 2 is an internal bus control circuit, 3 is a transfer direction control circuit, 4 is a data transfer path determining circuit,
5 is a status information register Wr, 6 is a data bus, and 7 is a status bus.

8 is a transfer FF information control circuit, and 9 is an external interface bus.

First, you need to change whether the data transfer amount is 1 byte wide or 2 byte wide, and whether the data content is data information or not.
Or, how to distinguish between status information and status information will be explained.

The internal bus control circuit 2 recognizes the transmission path access information sent by the internal bus 1, and based on the transmission path access information, determines whether the transfer is from the master station to the slave station on the external interface bus 9. Alternatively, the total transfer direction control circuit 3 determines whether the transfer is from the slave station to the master station (7) in the 71F direction.

Based on the recognition information obtained from the internal bus control circuit 2, the data transfer amount determining circuit 4 determines whether the transfer data is 1 byte wide or 2 bytes wide.

When the data transfer amount determination circuit 4 determines that the data transfer is 1 byte wide, the status information register circuit 5 stores the status information to be sent out on the remaining 1 byte wide transmission path.

It is stored from a central processing unit (not shown) via an internal bus 1 and an internal bus control circuit 2.

The transfer information control circuit 8 determines the content of the transfer data on the 2-byte wide transmission line to be sent to the slave station via the external interface bus 9 based on the information given from the data transfer amount determining circuit 4 and the transfer direction control circuit 3. Is it data information?

Alternatively, it may be status information or a circuit that controls all switches.

Next, the operation of data on the transmission path in each data transfer will be explained.

FIG. 2 is a flowchart illustrating the flow of data on the external interface bus 9 in terms of content and transfer direction at a certain time.

In FIG. 2, e is the time axis, and a to d are the access contents transferred from the central processing unit via the internal bus 1 in correspondence with the time axes, respectively.

In 1-byte write access 2, as shown in 5g, 1-byte data information and 1-byte status information are sent from the master station to the slave station. In the 1-byte read access b, 1-byte data information and 1-byte status information are sent from the slave station to the master station, as shown by i. For 2-byte write access C, k
As shown in the figure, 2-byte data information is sent from the master station to the slave station. In the 2-byte read access d, 2-byte data information is sent from the slave station to the master station as shown in m.

Note that when the transmission line is not fully used.

As shown in f, h, j, fi, and n, 2-byte wide status information is transferred from the slave station to the master station on the transmission path, and the master station transfers the status information from the external interface bus 9 to the status information bus 7. , the status of the subordinate station lj! ! Data is transferred while being monitored through the internal bus 1.

(Effects of the Invention) As explained above, the present invention arbitrarily switches the transfer amount between 1-byte width and 2-byte width according to the data capacity, and when transferring 1-byte width, the remaining 1-byte width is used for transmission. By controlling the status information so that it can be loaded with the status information, there is an effect that data transfer can be made faster and more efficient.

Furthermore, by sending all of the status information to the remaining data transmission path, there is the effect that status information can be easily exchanged between the master station and the slave station.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data transfer switching control circuit due to a misfire. FIG. 2 is a flowchart showing the content and direction of data transferred between a master station and a slave station in data transfer. 1.6, 7.9...Bus 2...Internal bus control circuit 3...Transfer direction control circuit 4...Data transfer amount determining circuit 5...Status information Registration gate circuit 8...Transfer information Control circuit diagram 2

Claims (1)

[Claims] Instructs the data transfer width of the external interface bus that connects the master station and slave stations, which is composed of a 2-byte wide bidirectional data bus and a control bus consisting of multiple bits, to 1 byte width or 2 byte width. a byte width instruction, a transfer direction instruction for instructing the direction of data transfer on the external interface bus from the master station to the slave station or vice versa, and a data transfer byte width of the external interface bus of 1 byte width. At this time, an internal bus control circuit for sending a status information sending instruction to send status information onto the remaining 1-byte wide external interface bus, and a data transfer instruction from the internal bus control circuit. a data transfer amount determining circuit for holding transfer byte width determining information; a transfer direction control circuit for recognizing the data transfer direction determining information in accordance with the transfer direction instruction from the internal bus control circuit; Under the condition that the status information register circuit for temporarily storing the status information and the data transfer amount determination circuit indicate a 1-byte width transfer, the transfer direction control circuit controls the transfer direction in the transmission direction. In addition to displaying the data transfer direction, if an instruction to send the status information is sent from the internal bus control circuit, the status information register circuit transfers the status information to the remaining 1 byte of the external interface bus. Sending a transmission instruction, or accepting that the status information on the external interface bus is taken into the status information register circuit if the transfer direction control circuit indicates the data transfer direction as the reception direction. 1. A data transfer switching control circuit comprising: a transfer information control circuit for sending an instruction.