JPS59107694A - Decentralized control system of automatic exchange - Google Patents
Decentralized control system of automatic exchangeInfo
- Publication number
- JPS59107694A JPS59107694A JP21665682A JP21665682A JPS59107694A JP S59107694 A JPS59107694 A JP S59107694A JP 21665682 A JP21665682 A JP 21665682A JP 21665682 A JP21665682 A JP 21665682A JP S59107694 A JPS59107694 A JP S59107694A
- Authority
- JP
- Japan
- Prior art keywords
- processor
- control
- processors
- information
- signal control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q3/00—Selecting arrangements
- H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
- H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
- H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
- H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
- H04Q3/5455—Multi-processor, parallelism, distributed systems
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Exchange Systems With Centralized Control (AREA)
Abstract
Description
【発明の詳細な説明】
制御回路を構成する，所謂，自動交換機の分散制御方式
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a distributed control system for so-called automatic switching equipment, which constitutes a control circuit.
従来，呼の状態遷移を制御する複数の接続制御プロセッ
サと，通話路機器の制御を行なう複数の信号制御プロセ
ッサとを主たる構成要素とする自る呼の状態情報を記憶
させる一時記憶メモリが設けられている。信号制御プロ
セッサは，通話路機器の状態変化を検出するとこの状態
変化情報と上記呼の状態情報とを接続制御プロセッサに
対して情報転送し，接続制御プロセッサは，転送された
上記情報を分析し，呼に関係する各通話路機器に対して
状態遷移を指示するために，その通話路機器が収容され
た信号制御プロセッサに状態遷移情報を転送していた。Conventionally, temporary storage memory has been provided to store call state information, the main components of which are a plurality of connection control processors that control call state transitions and a plurality of signal control processors that control communication path equipment. ing. When the signal control processor detects a change in the state of the communication path equipment, the signal control processor transfers this state change information and the call state information to the connection control processor, and the connection control processor analyzes the transferred information, In order to instruct state transition to each channel device involved in the call, state transition information was transferred to the signal control processor in which the channel device was accommodated.
寸た。このとき信号制御ノロセ、すに設けられた一時記
憶メモリには、状態遷移情報によって新しい呼の状態情
報が記憶される。Dimensions. At this time, new call state information is stored in the temporary storage memory provided at the signal control station based on the state transition information.
このように、従来の方式では、一つの呼に関する各通話
路機器ごとに現在における呼の状態情報を有しているた
め、２つ以上の通話路機器での状態変化が同時に検出さ
れた場合５２つ以上の接続制御プロセッサに状態変化情
報が転送されるので。In this way, in the conventional system, each channel device related to one call has current call state information, so if a change in the state of two or more channel devices is detected at the same time, 52 Because state change information is transferred to more than one connection control processor.
相互の調整をとるための複Ｋｆな手段が必要であった。Multiple means of mutual coordination were needed.
また、信号制御プロセッサと接続制御プロセッサ間の大
量の情報転送が必要になシ、それら各プロセッサは情報
転送処理に多大の時間を要するという欠点があった。Another disadvantage is that a large amount of information must be transferred between the signal control processor and the connection control processor, and each of these processors requires a large amount of time to process the information transfer.
本発明の目的は、上記従来の欠点を解決し、自動交換機
の規模によらない拡張性に富んだ自動交換機の分散制御
方式を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional drawbacks and to provide a distributed control system for automatic exchanges that is highly expandable regardless of the scale of the automatic exchange.
本発明によれば、呼の状態遷移を制御する複数の接続制
御プロセッサと８通話路機器の制御を行なう複数の信号
制御プロセッサとを主たるプロセッサとする自動交換機
の分散制御方式に於いて。According to the present invention, there is provided a distributed control system for an automatic switching system in which the main processors are a plurality of connection control processors that control call state transitions and a plurality of signal control processors that control eight channel devices.
呼の状態情報等を記憶させる共通メモリを設けると共に
、前記信号制御プロセッサごとに設けられた一時記憶メ
モリと前記共通メモリとの間の情報転送を前記信号制御
プロセッサとは独立に行々う信号制御情報転送プロセッ
サと、前記接続制御プロセッサごとに設けられた一時記
憶メモリと前記共通メモリとの間の情報転送を前記接続
制御プロセッサとは独立に行なう接続制御情報転送プロ
セッサを設けたことを特徴とする自動交換機の分散制御
方式が得られる。！た９本発明では、上記共通メモリに
のみ呼の状態情報を記憶させる自動交換機の分散制御方
式が得られる。A signal control system that provides a common memory for storing call status information, etc., and performs information transfer between a temporary storage memory provided for each signal control processor and the common memory independently of the signal control processor. A connection control information transfer processor is provided that transfers information between an information transfer processor, a temporary storage memory provided for each connection control processor, and the common memory independently of the connection control processor. A distributed control system for automatic switching equipment is obtained. ! According to the present invention, there is provided a distributed control system for automatic switching equipment in which call status information is stored only in the common memory.
次に本発明の実施例について図面を参照して説明する。Next, embodiments of the present invention will be described with reference to the drawings.
図面は本発明による自動交換機の分散制御方式の一実施
例の構成を示したブロック図である。図において、接続
制御プロセッサ１．−１ 、１−２〜１−には、一時的
な情報を記憶する一時記憶メモリ２−１ 、２−２〜２
−にのほかに、制御プログラムを記憶するためのメモリ
（図示せず）と、交換様の動作土必要となるシステムデ
ータ、局データを記憶するメモリ（図示せず）とを有す
る。接続制御情報転送プロセッサ３−１．３−２〜３−
ｔは接続制御プロセッサの一時記憶メモリ２−１゜２−
２〜２−にと共通メモリ４との間の情報転送を接続制御
プロセッサ１−１．１−２〜１−にとは独立に行なう。The drawing is a block diagram showing the configuration of an embodiment of the distributed control system for automatic switching equipment according to the present invention. In the figure, connection control processor 1. -1, 1-2 to 1- are temporary memory memories 2-1, 2-2 to 2 for storing temporary information.
- In addition to the above, it has a memory (not shown) for storing a control program, and a memory (not shown) for storing system data and station data required for operation of the replacement. Connection control information transfer processor 3-1.3-2 to 3-
t is the temporary storage memory 2-1゜2- of the connection control processor
2 to 2- and the common memory 4 are performed independently of the connection control processors 1-1, 1-2 to 1-.
スイッチ制御プロセッサ５は。The switch control processor 5 is.
共通メモリ４上に格納されたスイッチ制御情報を読み出
し２通話路スイッチ１ｏを制御する。信号制御情報転送
ノロセッサ６−１．６−２〜６−ｍは信号制御プロセッ
サの一時記憶メモリ７−１゜７−２〜７−ｎと共通メモ
リ４との間の情報転送を信号制御プロセッサ８−１．８
−２〜８−ｎとは独立に行なう。信号制御ｆｌｌｌプロ
セッサ８−１゜８−２〜８−ｎは、一時的なｔｆｊ報を
記憶する上記一時記憶メモリ７−１．７−２〜７−ｎの
ほかに。The switch control information stored in the common memory 4 is read out and the 2-channel switch 1o is controlled. The signal control information transfer processors 6-1, 6-2 to 6-m transfer information between the signal control processor temporary storage memories 7-1, 7-2 to 7-n and the common memory 4. -1.8
-2 to 8-n are performed independently. The signal control full processors 8-1, 8-2 to 8-n, in addition to the temporary storage memories 7-1, 7-2 to 7-n, which store temporary tfj information.
制御プログラムを記憶するだめのメモリ（図示せず）を
有し、各々の信号制御プロセッサ８−１゜８−２〜８−
ｎに収容された通話路機器９−１゜９−２〜９−ｎを制
御する。なお、共通メモリ４には呼の状態情報も格納さ
れている。Each signal control processor 8-1, 8-2 to 8- has a memory (not shown) for storing a control program.
Controls the communication path devices 9-1, 9-2 to 9-n housed in the communication path device 9-1. Note that the common memory 4 also stores call status information.
以下に実際の呼制御に於ける制御動作について説明する
。信号制御プロセッサ８は２通話路機器９の状態変化を
検出すると、その状態変化情報を信号制御プロセッサの
一時記憶メモリ７に書き込み、信号制御情報転送プロセ
ッサ６に対して転送要求を伝える。信号制御情報転送プ
ロセッサ６は。Control operations in actual call control will be explained below. When the signal control processor 8 detects a change in the state of the two-channel device 9, the signal control processor 8 writes the state change information into the temporary storage memory 7 of the signal control processor and transmits a transfer request to the signal control information transfer processor 6. The signal control information transfer processor 6 is.
この転送要求を受けると状態変化情報を読み出し。When this transfer request is received, the state change information is read.
共通メモリ４に設けられた対応する呼制御情報エリアの
状態変化情報登録エリアに書き込む。接続制御情報転送
プロセッサ３は、この状態変化情報の登録を検出し、呼
制御情報エリアの必要な情報（呼の状態情報と状態変化
情報を含む）を編集して接続制御プロセッサの一時記憶
メモリ２に書き込む。このように、接続制御情報転送プ
ロセッサ３に情報の編集機能を付与することによシ、接
続制御グロセッサ１が無駄な処理を行なうことを防ぐこ
とができる。接続制御ゾロセッサ１は、その一時記憶メ
モリ２に書きこまれた情報をもとにして呼の状態遷移を
決定し、呼に関係する通話路機器の制御指示情報、すな
わち状態遷移情報を接続プロセッサの一時記憶メモリ２
に書き込む。この通話路機器制御指示情報は、接続制御
情報転送プロセッサ３によって、共通メモリ４の呼制御
情報エリアの通話路機器制御情報エリアに書き込捷れる
。これによって、共通メモリには新しい呼の状態情報が
記憶される。信号制御情報転送プロセッサ６は、この通
話路機器制御指示情報を読み出し。It is written in the state change information registration area of the corresponding call control information area provided in the common memory 4. The connection control information transfer processor 3 detects the registration of this status change information, edits the necessary information (including call status information and status change information) in the call control information area, and stores the edited information in the temporary storage memory 2 of the connection control processor. write to. In this manner, by providing the connection control information transfer processor 3 with an information editing function, it is possible to prevent the connection control gross processor 1 from performing unnecessary processing. The connection control processor 1 determines the state transition of the call based on the information written in the temporary storage memory 2, and transmits the control instruction information of the channel equipment related to the call, that is, the state transition information to the connection processor. Temporary memory 2
write to. This channel equipment control instruction information is written into the channel equipment control information area of the call control information area of the common memory 4 by the connection control information transfer processor 3. This causes new call status information to be stored in the common memory. The signal control information transfer processor 6 reads this channel equipment control instruction information.
この通話路機器９が収容されている信号制御ゾロセッサ
の一時記憶メモリ７に書き込む。信号制御プロセッサ８
はこの通話路機器制御指示情報をもとにして通話路機器
９を制御する。This communication path equipment 9 is written into the temporary storage memory 7 of the signal control processor in which the communication path equipment 9 is accommodated. Signal control processor 8
controls the communication path equipment 9 based on this communication path equipment control instruction information.
以上、簡単に呼制御の方式について説明したが。The above is a brief explanation of the call control method.
２つ以上の通話路機器９での状態変化が同時に検出され
ることにより発生した状態変化情報を、信号制御情報転
送プロセッサ６により共通メモリ４の呼制御情報エリア
に順に記憶させておくことによシ、接続制御プロセッザ
１の中の１つが、１回の処理で１つの呼の複数の状態変
化情報を分析して呼制御を行なうことも可能である。ま
た、接続制御プロセッサ１．信号制御プロセッサ８．接
続制御情報転送プロセッサ２．及び信号制御情報転送プ
ロセッサ６などは、最近、集積度の高まっている１チツ
ゾのＴ、ＳＩで構成することも可能であシ。By sequentially storing state change information generated by simultaneous detection of state changes in two or more call path devices 9 in the call control information area of the common memory 4 by the signal control information transfer processor 6. It is also possible for one of the connection control processors 1 to perform call control by analyzing a plurality of state change information of one call in one process. Furthermore, the connection control processor 1. Signal control processor8. Connection control information transfer processor 2. The signal control information transfer processor 6, etc. can also be constructed from a single-chip T or SI, which has recently become more integrated.
さらにそれぞれのプロセッサ間は完全な階層構造になっ
ている。したがって処理能力の向上が容易で信頼性の高
い自動交換機を構成できる。Furthermore, each processor has a complete hierarchical structure. Therefore, it is possible to construct a highly reliable automatic switching system whose processing capacity can be easily improved.
以上の説明で明らかなように１本発明によれば。According to one aspect of the present invention, as is clear from the above description.
処理能力の小さな多数のプロセッサを階層的に構成する
ことによシ、処理能力が大きく拡張性に富んだ信頼性の
高い自動交換機の分散制御方式を実現できる。By configuring a large number of processors with small processing capacity in a hierarchical manner, it is possible to realize a highly reliable distributed control system for automatic exchanges with large processing capacity and high expandability.
図面は本発明による自動交換機の分散制御方式の一実施
例の構成を示したプロ、り図である。
］−］１．１−２〜１−ｋ・・接続制御プロセッサ。
２−１．２−２〜２−ｋ・・・接続制御プロセッサの一
時記憶メモリ、３−１．３−２〜３−４・・・接続制御
情報転送グロセノサ、４・・・共通メモリ、５・・・ス
イッチ制御プロセッサｌ ’） −１，１６−２〜６−
ｍ・・・信号制御情報転送プロセッサ、 ７−１． 、
７−２〜７−ｎ・・・信号制御プロセッサの一時記憶メ
モリ。
８−１．８−２〜８−ｎ・・・信号制御プロセッサ。
９−１．９−２〜９−ｎ・・・通話路機器、１０・・・
通話路スイッチ。
５１The drawing is a schematic diagram showing the configuration of an embodiment of the distributed control system for automatic switching equipment according to the present invention. ]-]1.1-2 to 1-k...Connection control processor. 2-1.2-2 to 2-k... Connection control processor temporary storage memory, 3-1.3-2 to 3-4... Connection control information transfer grossenosa, 4... Common memory, 5 ...Switch control processor l') -1, 16-2 to 6-
m...signal control information transfer processor, 7-1. ,
7-2 to 7-n: Temporary storage memory of the signal control processor. 8-1.8-2 to 8-n...Signal control processor. 9-1.9-2 to 9-n...Call path equipment, 10...
Call path switch. 51
Claims (1)
と２通話路機器の制御を行なう複数の信号制御プロセッ
サとを主たるプロセッサとする自動交換機の分散制御方
式に於いて、呼の状態情報等を記憶させる共通メモリを
設けると共に、前記信号制御プロセッサごとに設けられ
た一時記憶メモリと前記共通メモリとの間の情報転送を
前記信号制御プロセッサとは独立に行なう信号制御情報
転送プロセッサと、前記接続制御プロセッサごとに設け
られた一時記憶メモリと前記共通メモリとの間の情報転
送を前記接続制御プロセッサとは独立に行なう接続制御
情報転送プロセッサを設けたことを特徴とする自動交換
機の分散制御方式。 ２ 前記共通メモリにのみ前記呼の状態情報を記憶させ
る特許請求の範囲第１項記載の自動交換機の分散制御方
式。[Scope of Claims] 1. In a distributed control system for an automatic switching system in which the main processors are a plurality of connection control processors that control call state transitions and a plurality of signal control processors that control call path equipment, A signal control information transfer processor that includes a common memory for storing state information, etc. of the signal control processor, and transfers information between the temporary storage memory provided for each signal control processor and the common memory independently of the signal control processor. and a connection control information transfer processor that transfers information between the temporary storage memory provided for each connection control processor and the common memory independently of the connection control processor. Distributed control method. 2. A distributed control system for an automatic switching system according to claim 1, wherein the call status information is stored only in the common memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21665682A JPS59107694A (en) | 1982-12-10 | 1982-12-10 | Decentralized control system of automatic exchange |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21665682A JPS59107694A (en) | 1982-12-10 | 1982-12-10 | Decentralized control system of automatic exchange |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59107694A true JPS59107694A (en) | 1984-06-21 |
Family
ID=16691870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21665682A Pending JPS59107694A (en) | 1982-12-10 | 1982-12-10 | Decentralized control system of automatic exchange |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59107694A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100974513B1 (en) | 2009-07-13 | 2010-08-10 | 신세계건설(주) | Caisson type pile method |
-
1982
- 1982-12-10 JP JP21665682A patent/JPS59107694A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100974513B1 (en) | 2009-07-13 | 2010-08-10 | 신세계건설(주) | Caisson type pile method |
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