JPS59205662A - Inter-processor information transfer priority system - Google Patents

Abstract

PURPOSE:To give the priority to the transfer of information among processors by opening and closing a gate means of an information transfer route from the 1st to the 2nd processor group under the control of a general processor. CONSTITUTION:The information is transferred to the 2nd processor groups 110, 111 and 11n from the 1st processor groups 100, 101 and 10n via transfer routes 130 and 131. In this case, a gate circuit 140 is controlled by a general processor 120. For instance, the processor 120 wants to inhibit the transfer of data from the 1st processor groups and to transfer the data to the 2nd processor groups. In such a case, a control line is set at a high level of voltage and therefore the output of an AND element of the circuit 140 is set a low level of voltage. Thus the data of the 1st processor groups are not transferred, and only the data of the processor 120 is transferred. Thus it is possible to give the priority to the transfer of information among processors by providing a gate means to the transfer route to control the transfer of information among processors.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inter-processor information transfer priority system in a distributed control system.

Conventionally, information transfer between processors has not been prioritized. Therefore, the general processor that monitors and controls the entire system is also in the same position as each processor group, and information is transferred to other processor groups on a first-come, first-served basis, so urgent processing from the general processor is delayed. Also, competition occurs with the processor group. Alternatively, there was a problem in that they were unable to transfer information to each other and backed down.

An object of the present invention is to open and close gate means of an information transfer path from a first processor to a second processor group under control from a general processor that monitors and controls the entire distributed control system. An object of the present invention is to provide an inter-processor information transfer priority system that solves all of the above problems and makes it possible to give priority to information transfer between processors.

The inter-processor information transfer priority method according to the present invention divides a processor group into a plurality of control function distribution films by interconnecting a plurality of processors having the same control function by an information transfer path, and connects the processor group to the processor group by the information transfer path. In a distributed control system including a connected general processor that monitors and controls the entire system, the gate means gives priority to information transfer from the general processor over information transfer from the first group to the second group of the processor groups. The gate means is disposed in a transfer path, and the gate means is opened and closed from the general processor.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram for explaining one embodiment of the present invention. In the same figure, reference numerals 100, 101.10n indicate a first processor group 110.111 that executes the same control function.
．． lln is a second processor group that executes other same control functions, 120 is a general processor that monitors and controls the entire system, and 130 and 131 are transfer paths for transferring information (data) between each processor. , and 140 is the first
The gate circuits that allow data transfer from the first processor group 100 to 10n to the second processor group 110 to lln under the control of the processor 120 are shown respectively.

FIG. 2 shows a specific configuration example of the gate circuit 140 in FIG.
a data line from to the second processor group 110 to 10n;
210 to 217 are the first processor group 1 of the transfer path 131;
Data lines 250 to 257 are data lines from 00 to Ion to the second processor group 110 to lln, and data lines 250 to 257 are data lines on the second processor group side of the transfer path 131. Inverters 220 to 227 receive information from the control line 200. 2
30-237 are AND elements and inverters 220-227
and information on data lines 210 to 217 from the first processor group 100 to Ion are input. 240-2
Reference numeral 47 denotes an OR element, which inputs the outputs of the AND elements 230 to 237 and the information on the data lines 201 to 208 from the processor 20, and outputs the data lines 250 to 257 to the second processor group 110 to lln. It has become.

Here, in the normal state υ, data transfer from the processor 20 to the second processor group 110 to lln and data transfer from the first processor group 100 to 10n to the second processor group 11
If there is no need to give priority to data transfer to 0 to lln, the control line 200 will be at a low voltage level, so the inverters 220 to 2 of the AND elements 230 to 237
The input on the 27 side becomes a high voltage level, and if there is data transfer from the first processor group 100 to 10n, the input on the data line 21
The information from 0 to 217 is directly transferred to AND elements 230 to 237
The output is

In this state, data from the processor 120 can also be transferred to the second processor group 110-lln.

Further, the processor 120 is connected to the first processor group 400 to
If it is desired to prohibit data transfer from 10n and transfer data to the second processor group 110-lln, control line 200 is set to a high voltage level. At this time, the outputs of the inverters 220 to 227 are at a low voltage level, and the outputs of the AND elements 230 to 237 are at a low voltage level and no longer output. Therefore, until the control line 200t is returned to the low voltage level under the control of the processor 120, data from the first processor group 100 to Ion will no longer be transferred, and only data from the processor 120 will be transferred.

As described above, the present invention can give priority to information transfer between processors by providing gate means for controlling information transfer between processors on the information transfer path.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing one embodiment of the present invention, and FIG.
FIG. 3 is a configuration diagram showing a specific example of the gate circuit in the figure. 1
00-10n...First processor L 110
~lln...Second processor group, 120...
. . . general processor, 130, 131 . . . - information transfer path, 140 . . . gate circuit.

Claims (1)

[Claims] A general processor that distributes a plurality of control functions to a processor group formed by interconnecting a plurality of processors having the same control function through an information transfer path, and is connected to the processor group through an information transfer path and monitors and controls the entire system. In the distributed control system, a gate means for giving priority to information transfer from the general processor over information transfer from the first group to the second group of the processor groups is disposed on the information transfer path, and the gate means The inter-processor information transfer priority method is characterized in that the information transfer priority method is opened and closed from the general processor.