JPH01177464U - - Google Patents
Info
- Publication number
- JPH01177464U JPH01177464U JP7502588U JP7502588U JPH01177464U JP H01177464 U JPH01177464 U JP H01177464U JP 7502588 U JP7502588 U JP 7502588U JP 7502588 U JP7502588 U JP 7502588U JP H01177464 U JPH01177464 U JP H01177464U
- Authority
- JP
- Japan
- Prior art keywords
- low
- data
- read
- phase difference
- pass filter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 1
Landscapes
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
第１図はこの考案の一実施例である読出データ
処理装置のブロツク図、第２図は従来のＶＦＯ回
路のブロツク図である。
１……位相検出器、２……読出データ、３……
ＶＦＯクロツク、４ａ……引込みＬＰＦ、４ｂ…
…読取りＬＰＦ、４ｃ……第１のＬＰＦ、４ｄ…
…第２のＬＰＦ、５……ＶＣＯ、６……分周器、
７……データセパレータ、８……データ、９……
ウインド、１０……Ｓｙｎｃ検出回路、１１……
切換え信号、１２……切換え手段、１５……選択
手段、１７……エラー検出器。
FIG. 1 is a block diagram of a read data processing device which is an embodiment of this invention, and FIG. 2 is a block diagram of a conventional VFO circuit. 1... Phase detector, 2... Read data, 3...
VFO clock, 4a... Retractable LPF, 4b...
...Read LPF, 4c...First LPF, 4d...
...Second LPF, 5...VCO, 6...Frequency divider,
7...Data separator, 8...Data, 9...
Window, 10...Sync detection circuit, 11...
Switching signal, 12...Switching means, 15...Selecting means, 17...Error detector.
Claims (1)
位相差を検出する位相検出器と、データの引込み
時に上記位相差を積分する応答性の速い引込みロ
ーパスフイルタと、データの読み取り時に上記位
相差を積分する応答性の遅い読取りローパスフイ
ルタと、上記引込みローパルフイルタと読取りロ
ーパスフイルタとを選択する選択手段と、上記各
ローパスフイルタにより積分された位相差によつ
て出力周波数を変調する電圧制御発振器と、出力
周波数を１／Ｎに分周する分周器と、分周された
出力周波数と上記読出データとからデータ及びウ
インドを生成するデータセパレータと、このデー
タセパレータの出力により上記ＶＦＯクロツクを
生成するＳｙｎｃ検出器とからなる読出データ処
理装置において、上記読取りローパスフイルタを
、応答性の速い第１のローパスフイルタと応答性
の遅い第２のローパスフイルタとから構成し、上
記第１、第２のローパスフイルタの出力を選択し
て上記電圧制御発振器に出力する切換え手段を備
えたことを特徴とする読出データ処理装置。 A phase detector that detects the phase difference between data read from the storage device and the VFO clock, a fast-responsive pull-in low-pass filter that integrates the phase difference when reading data, and a response that integrates the phase difference when reading data. a voltage-controlled oscillator that modulates the output frequency according to the phase difference integrated by each of the low-pass filters; a frequency divider that divides the frequency to 1/N, a data separator that generates data and a window from the divided output frequency and the read data, and a Sync detector that generates the VFO clock from the output of the data separator. In the read data processing device, the read low-pass filter is composed of a first low-pass filter with a fast response and a second low-pass filter with a slow response, and the outputs of the first and second low-pass filters are A read data processing device comprising: switching means for selecting and outputting the selected voltage to the voltage controlled oscillator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7502588U JPH01177464U (en) | 1988-06-06 | 1988-06-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7502588U JPH01177464U (en) | 1988-06-06 | 1988-06-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01177464U true JPH01177464U (en) | 1989-12-19 |
Family
ID=31300104
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7502588U Pending JPH01177464U (en) | 1988-06-06 | 1988-06-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01177464U (en) |
-
1988
- 1988-06-06 JP JP7502588U patent/JPH01177464U/ja active Pending
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