JPH01176942U - - Google Patents

Info

Publication number
JPH01176942U
JPH01176942U JP7351888U JP7351888U JPH01176942U JP H01176942 U JPH01176942 U JP H01176942U JP 7351888 U JP7351888 U JP 7351888U JP 7351888 U JP7351888 U JP 7351888U JP H01176942 U JPH01176942 U JP H01176942U
Authority
JP
Japan
Prior art keywords
integrated circuit
groove
coating layer
resin coating
circuit board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7351888U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7351888U priority Critical patent/JPH01176942U/ja
Publication of JPH01176942U publication Critical patent/JPH01176942U/ja
Pending legal-status Critical Current

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例を示す拡大縦断側
面図、第2図は同上の回路基板の一部を切欠した
拡大斜視図、第3図は他の実施例を示す拡大縦断
側面図、第4図は従来の混成集積回路装置の一例
を示す拡大縦断側面図である。 11…回路基板、12…回路電極、13…集積
回路、14…ワイヤー、15…溝、16…樹脂コ
ーテイング層、17…電極、18…内部配線。
FIG. 1 is an enlarged vertical side view showing one embodiment of the invention, FIG. 2 is an enlarged perspective view with a part of the same circuit board cut away, and FIG. 3 is an enlarged longitudinal side view showing another embodiment. FIG. 4 is an enlarged longitudinal sectional side view showing an example of a conventional hybrid integrated circuit device. DESCRIPTION OF SYMBOLS 11... Circuit board, 12... Circuit electrode, 13... Integrated circuit, 14... Wire, 15... Groove, 16... Resin coating layer, 17... Electrode, 18... Internal wiring.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 回路基板上に集積回路を装着したものにおいて
、該集積回路の周囲の基板上に溝を形成し、この
溝を含む集積回路全体を覆う樹脂コーテイング層
を設けたことを特徴とする混成集積回路装置。
A hybrid integrated circuit device in which an integrated circuit is mounted on a circuit board, characterized in that a groove is formed on the substrate around the integrated circuit, and a resin coating layer is provided to cover the entire integrated circuit including the groove. .
JP7351888U 1988-06-02 1988-06-02 Pending JPH01176942U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7351888U JPH01176942U (en) 1988-06-02 1988-06-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7351888U JPH01176942U (en) 1988-06-02 1988-06-02

Publications (1)

Publication Number Publication Date
JPH01176942U true JPH01176942U (en) 1989-12-18

Family

ID=31298659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7351888U Pending JPH01176942U (en) 1988-06-02 1988-06-02

Country Status (1)

Country Link
JP (1) JPH01176942U (en)

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