JPH01176115A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the increase in power consumption and the deterioration or destruction of an element by giving a signal through a delay circuit to each gate and eliminating a through-current flowing from the P-channel to the N- channel element at the output state change. CONSTITUTION:Inverters I2, I3 are provided after an inverter to apply waveform shaping, then a high dielectric strength N-channel MOSFETM2 is turned on to retard the final stage high dielectric P-channel MOSFETM6 to be turned on. The signal from the inverter 11 decreases not only the gm of N-channel MOSFETsM1, M2 and there is no delay in the timing when the MOSFETM1 is turned on and the MOSFETM2 is turned off, the P-channel MOSFETM6 is turned off simultaneously when an input signal IN0 is changed. Similarly, only the ON of the high dielectric strength N-channel NOSFETM3 is retarded by decreasing the (gm) of the P-channel MOSFET through the signal in an inverter I5 with a slow leading similarly. Since the timing from OFF to ON of the N-channel MOSFETM3 and the P-channel MOSFETM6 is deviated, the ON/OFF period is eliminated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit that handles high voltage and large current, and in particular, from low voltage CMOS circuits to high voltage CM circuits.
The present invention relates to a level shift circuit that converts a level to an OS circuit.

[Conventional technology]

An example of a conventional level shift circuit of this type is shown in FIG. Figure (a) is a circuit diagram, M13 to M15 are high voltage Nch MOSFETs, M16 to M18 are high voltage PchM
It is composed of O3FET. In addition, FIG. 6(b) shows the operating waveforms of each part. Low voltage system signal 20 (INO)
When becomes “H”, NchMO3FETM14 turns on,
NchMOSFETM13°Ml5 is turned off. At this time, the potential of the node 23 decreases, so the PchMOSFETM
16 and Ml8 are turned on, the potentials of the node 22 and the output terminal 24 are increased, and the PchMO3FETM17 is turned off. When the signal 20 (INO) becomes "H", the opposite operation to the above occurs, and the NchMOSFETM13. M1=5 and PchM
O3FETMI 7 turns on, NchMO3FETM1
4 and PchMO3FETM16. Ml 8 is turned off and the potential at the output terminal 24 drops.

[Problem that the invention seeks to solve]

The conventional level shift circuit described above has a final stage NchM
ON of OSFETM15 and PchMOSFETM18
Since the off-switching occurs at the same timing, an on-on period occurs when switching, and because the current starting ability is large in the final stage, a fairly large through current flows. For this reason, an increase in power consumption and a large current due to a through current may cause deterioration or destruction of the element.

[Means for solving problems]

The level shift circuit of the present invention is a P-channel type MOSFE.
A signal passed through a delay circuit is input from the P channel side of a buffer that connects the T and N channel MOSFET drains to each gate of the N channel side, and when the output state changes, the signal is input from the P channel side to the N channel side. It is characterized by eliminating the through current that flows.

〔Example〕

Next, the present invention will be explained in more detail with reference to the drawings.

FIGS. 1(a) and 1(b) are a circuit diagram and an operation waveform diagram of an embodiment of the present invention.

The input signal is applied to the slow falling inverter Il+Is, and the output of the inverter 11 is applied to the inverter I2゜■,
is applied to the gate of Nch MOSFET M1 through an inverter, and is applied to the gate of Nch MOSFET M1 through
given to the gate of 2. NchMOSFETMI and P
It is connected in series with chMoSFETM4, and NchMO
3FETM2 and PchMOSFETM5 are also connected in series, and connection point 5 is connected to the gate of PchMO3FETM4.
Further, connection points 4 are connected to the gates of the PchMOSFETM5 in a cross-connected manner. From connection point 5, Pch
A signal is applied to the gate of the output MOSFET M6.

The output of the inverter is the inverter. , a signal is applied to the gate of the Nch output MO3FETM3 via the air. The Pch output MOSFET M6 and the Nch output MO3FETM3 are connected in series, and an output is taken out to the output terminal 6 from their common drain connection point.

The low voltage system inverter is an inverter with a slow fall, and the gm of the Nch MO8 is lowered to delay the fall. The delay time to avoid through current is 20n.
This delay time can be obtained by increasing the channel length and lowering g. After this inverter, one to several stages of inverter I2. Waveform shaping is performed by adding Is.

As a result, the high voltage Nch MOSFET M2 is turned on, and it is possible to delay the turning on of the final stage high voltage Pch MOSFET M6. The one that lowered the gm of the inverter was NchMOSFETM1. Because it's not just M2,
There is no delay in the timing when MO3FETMI turns on and MO3FETM2 turns off, so PchMO
3FETM6 turns off at the same time as the input signal INO changes. Similarly, inverter I, which has a slow rise, and Pch inside
High voltage NchMO can be achieved by lowering g, l of MO3FET.
Only the turning on of SFETM3 can be delayed. Nch
By shifting the timing of each of MOSFET M3 and PchMOSFETM6 from off to on by 20 nS, the on-on period can be eliminated.

FIGS. 2(a) and 2(b) are a circuit diagram and an operation waveform diagram of another embodiment of the present invention. While the embodiment of FIG. 1 has two delay circuits (inverters L and Is) and independently determines the rise and fall of the output, this embodiment has one delay circuit.
Final stage high voltage PchMO3FETM with two delay circuits 27
12 and high voltage Nch MOSFET M9, the timing delay from off to on is determined. Although it is not possible to independently optimize the rise and fall delays of high-voltage output, there is an advantage in that there is only one parameter to be adjusted, making it easier.

[Effect of the invention] As explained above, the final stage high voltage Pch MOSFET
By delaying the timing from OFF to ON of each high-voltage Nch MOS FET, the on-on period is eliminated, and the large through-current that normally flows in the final stage due to its large current drive capability is eliminated. Can be done.

For AC type plasma display, IM at 40V
Switching is performed at about Hz. A conventional IC with a high voltage output of 64 circuits consumes approximately 1.6 W of power, including approximately 0.8 W of power due to the through current and approximately 0.8 W of power due to the panel load. By utilizing the present invention, the power due to the through current can be reduced to "0", and the power consumption of the IC can be reduced to 0.8W, which is half of the conventional power consumption.

As a result, the conventional use of expensive packages with good heat dissipation, such as ceramic packages, can now be replaced with inexpensive molded packages, resulting in significant cost reductions.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are a circuit diagram and operating waveform diagram of one embodiment of the present invention, and FIGS. 2(a) and (b) are a circuit diagram and operating waveform diagram of another embodiment of the present invention. , Figure 3(a). (b) is a circuit diagram and an operation waveform diagram of a conventional level shift circuit. Ml~M3. M7-M9. M13~M'l 5...Dan...
High withstand voltage N++Nell type MOSFET%M4~M62M
1o~-Ml 2. Ml 6 to M18...High voltage P-channel MOSFET, 1. ~ Engineering 1...
Low voltage inverter, NANDl...Low voltage NAND, N0R1...Low voltage NOR, 7
, 18, 20... Input terminal low voltage type level, 6
, 15.24... High voltage output terminal, 8.16.2
5...Ground, 9,17゜26...
・High voltage power supply, 27...delay circuit. Agent Patent Attorney Oto Uchihara

Claims (1)

[Claims] P-channel type MOSFET and N-channel type MOSFET
In a CMOS circuit composed of
The output of a buffer circuit that connects the drains of an SFET and an N-channel MOSFET drives one MOSFET of an output circuit that connects a P-channel MOSFET and an N-channel MOSFET in series, and the other MOSFET is driven by another drive circuit. 1. A semiconductor integrated circuit, wherein output generation timings of said buffer and said other driving circuit are staggered.