JPH01175257A - Manufacture of mis semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a tungsten gate electrode from being side-etched and to prevent an irregularity and a deterioration of the performance of an element by a method wherein, after a gate insulating film and a tungsten layer have been formed on a semiconductor substrate and this assembly has been thermally nitrified in ammonia gas, a patterning operation is executed by reactive ion etching using a fluorine-based gas. CONSTITUTION:A gate oxide film 5 by thermal oxidation is formed in a device formation region 4 on a p<-> type Si substrate 1; then, a W layer 106 is formed by a sputtering method. Then, this assembly is heat-treated in ammonia gas; a tungsten nitride layer 7 is formed. Then, an SiO2 mask film 108 is formed; a resist pattern 9 corresponding to a gate electrode is formed on it; an SiO2 mask pattern 8 corresponding to the gate electrode is formed by making use of the resist pattern as a mask by an RIE operation using a gas of CHF3+CF4; in addition, the W layer 106 is patterned by making use of the mask pattern as a mask by the RIE operation using a gas ot SF6. By this setup, the side- etching amount e1 on the side of a W gate electrode 6 can be reduced to about 500-1000Angstrom or less.

Description

[Detailed Description of the Invention] [Summary] Regarding a method for manufacturing an MIS type semiconductor device, particularly a method for forming a tungsten gate electrode which is becoming finer, it is possible to prevent side etching of the tungsten gate electrode during patterning and to increase the width of the gate electrode. In order to prevent variations in device performance and deterioration caused by fluctuations and separation of the source/drain region from the gate edge, etc., when forming a tungsten gate electrode, a gate insulating film is formed on the semiconductor substrate, and the gate insulating film is formed on the semiconductor substrate. After forming a tungsten layer on the gate insulating film and thermally nitriding the tungsten layer in ammonia gas.

[Industrial Application Field] The present invention relates to a method for manufacturing an MIS type semiconductor device, and in particular to a method for manufacturing a tungsten gate electrode to be miniaturized. The present invention relates to a method of forming.

As MIS-type semiconductor devices become more highly integrated and the elements become smaller, the gate electrode width (equivalent to gate length) is becoming increasingly smaller, and the associated increase in gate electrode resistance is increasing. A problem arises in that the operating speed of the MIS type semiconductor device is reduced.

Conventionally, as a means to solve the above problem, refractory metal silicide, which has a resistivity that is about an order of magnitude lower than the polysilicon that was originally used, was used as the gate electrode material, but in recent years, even higher integration has been used. As technology advances, there is a demand for lower resistance gate electrodes. Therefore, in order to meet this demand, high melting point metal itself, which has a low specific resistance of about one-tenth to one-tenth that of high-melting point metal silicide, and in particular tungsten, which is thermally stable and suitable for the manufacturing process, was used as the gate electrode material. It is beginning to be used as a

[Conventional technology]

Tungsten (W)N used for the gate electrode is usually formed by sputtering, and the W layer 51 formed by this method has a diameter of 500 to 1000 along the deposition direction, as schematically shown in FIG. Columnar conjunctival thickness 2, about the size of a human, is formed in an aggregated crystalline structure.

Therefore, when patterning the tungsten layer, when a resist is directly deposited as a mask layer on the tungsten layer, contaminants in the resist pass through the tungsten layer along the grain boundaries of the columnar crystals. This contaminates the gate insulating film below the gate, resulting in performance deterioration such as a drop in gate breakdown voltage and fluctuations in dark voltage.

Furthermore, when attempting to form source/drain regions by implanting impurity ions as usual using the 88W gate electrode as a mask, the impurities are injected into the lower gate region along the crystal grain boundaries, resulting in a gap between the source and drain. This may cause performance deterioration such as short circuit.

Therefore, when manufacturing a MIS type semiconductor device having a W gate electrode, it is necessary to provide some kind of mask film on the W layer to eliminate the above problem.

Therefore, in the past, a silicon (Si) oxide-based insulating film such as silicon dioxide (SiO□) or phosphosilicate glass (PSG) was provided as a mask film, and the mask film was manufactured by the method described below.

That is, as shown in FIG. 4+a), for example, a gate oxide film 5 is formed on a p-type St substrate 1 consisting of a substrate or a well, and a thickness of, for example, 2000 to 3000 mm is formed on the gate oxide film 5 by sputtering. Form a W layer with a thickness of about 10 people, and then form a W layer with a thickness of about 2000 people on the W1i106.
After forming a mask film 108 made of a vapor phase grown silicon dioxide (CVD-Sing) film, a resist pattern 9 corresponding to the gate electrode pattern is formed on the 5in2 mask film 108, and then as shown in FIG. 4(b). As shown,
Using the resist pattern 9 as a mask, for example, trifluoride meta 7 (
The mask film 108 is patterned by reactive ion etching (RIE) using CHF3)+4 carbon fluoride (CF4) gas, and then sulfur hexafluoride (SF4) gas is used to pattern the mask film 108.
6) Alternatively, pattern the W layer 106 by performing RTE treatment using a fluorine-based gas such as nitrogen trifluoride (NF3),
A W gate electrode 6 having the 5i02 mask pattern 8 described above was formed thereon.

[Problem that the invention seeks to solve]

However, according to the conventional method, during the RIE process using the fluorine-based gas, the Si oxide mask film pattern formed on the W gate electrode 6, that is, the 5i02 mask pattern 8, contributes to the reaction, resulting in an isotropic reaction. The chemical etching reaction progresses strongly, and the side surface of the W gate electrode 6 is etched to a large extent (for example, about 0.3 to 0.4 μm) as shown by e2, resulting in the gate electrode width (corresponding to the gate length).
There was a problem that LG could not be formed with high precision.

Further, as shown in FIG. 4(C), the resist pattern 9
When forming a shallow n-type source region 10 and drain region 1) by ion-implanting an impurity such as arsenic (As'') using the mask film pattern 8 as a mask, the source region 10 and the drain region 1) are placed opposite each other. Since the end portion thereof is formed apart from the gate lower region 12 (separated portion 13), a problem arises in that the device operation is impaired.

Therefore, the present invention prevents side etching of the W gate electrode during patterning of the gate electrode in the manufacturing process of a MIS type semiconductor device having the W gate electrode.
The purpose of this is to prevent variations and deterioration in device performance caused by variations in gate electrode width and separation of source/drain regions from gate ends.

[Means for solving problems]

The above problem is solved by forming a tungsten gate electrode on a semiconductor substrate, forming a tungsten layer on the gate insulating film, and forming a tungsten gate electrode. The problem is solved by the method of manufacturing an MIS type semiconductor device according to the present invention, which includes a step of thermally nitriding the tungsten layer in ammonia gas and then patterning the tungsten layer by reactive ion etching treatment using a fluorine-based gas.

[For production]

That is, in the method of the present invention, the tungsten layer is thermally nitrided in ammonia gas and then buttered by RIE treatment.

Tungsten nitride (WN) or (WZN) is formed on the surface of the tungsten layer by the thermal nitriding, and at the same time, this nitriding reaction occurs along the grain boundaries of the columnar crystals formed in the tungsten layer along the aforementioned deposition direction. A wall layer of tungsten nitride (WN) or (6N) is formed at the grain boundary and reaches the bottom surface of the tungsten layer.
゛This tungsten nitride (WN) or (WJ) is fluorine (
In the RIE process using the F) type gas, etching progresses due to being bombarded by ions and radicals, but chemically there is almost no etching.

Therefore, in the above RIE process, the exposed portion of the mask film is rapidly etched, but the W layer in the lower region of the mask film, which is not bombarded by ions and radicals, is made of tungsten nitride formed at the grain boundaries. Since the (WN) or (w2N) wall layer prevents the chemical etching of W from proceeding in the lateral direction, the side etching width generated at the bottom of the mask film is 500 to 1000 mm, which corresponds to the grain size of the columnar W crystal. It can be suppressed.

Therefore, variations in the width of the gate electrode caused by the side etching are suppressed to a minimum, and at the same time, the source and drain regions formed using the mask film pattern provided on the gate electrode are separated from the lower gate region. Therefore, variations in device performance and the formation of non-operational devices are prevented.

〔Example〕

The present invention will be specifically explained below with reference to illustrated embodiments.

FIGS. 1(a) to 1(fl) are cross-sectional views of one embodiment of the method of the present invention, and FIGS. 2(a) to (C) are cross-sectional views of another embodiment of the method of the present invention.

Identical objects are indicated by the same reference numerals throughout the figures.

Refer to FIG. 1 tal When forming an MO8 semiconductor device having a W gate electrode by the method of the present invention, a p-type Si substrate 1 is defined and separated by a field oxide film 2 and a p-type channel stopper 3 below it. Using a normal substrate to be processed having a formation region 4, first, a gate oxide film 5 having a thickness of about 200 nm, for example, is formed by thermal oxidation on one surface of the Si substrate exposed in the element formation region 4, and then by normal sputtering. W is deposited on the substrate to a thickness of, for example, about 2,000 to 3,000 by a method.
A layer 10 thick is formed.

FIG. 1 (see BL) Next, the substrate was placed in ammonia gas (NH,) for 7
Heat at a temperature of 00 to 900℃ for about 20 minutes, and
A tungsten (WN) or (6N) layer 7 is formed on the surface of the W layer 106 and at the grain boundaries of the columnar W crystals 52 constituting the W layer 106 described above, with a thickness of, for example, 10 to 50 nm.

Refer to FIG. 1(C) Next, a 0Si0g mask film 108 with a thickness of about 2000 layers is formed on the tungsten nitride layer 7 by chemical vapor deposition (CVO method), and a resist pattern corresponding to the gate electrode is formed on the mask film 108. form 9.

Refer to FIG. 1(d). Next, using the resist pattern 9 as a mask, the mask film 108 is etched by RIE processing using a gas such as (CIIF3+CF) to ensure a selectivity with the W layer 106, so as to correspond to the gate electrode. A Si0g mask pattern 8 is formed.

Refer to FIG. 1(e). Next, using the above Sin and pattern 8 as a mask, for example, SF
WJi! by RIE treatment using b gas! 106 patterning is performed. By this RIE process, the W layer 106 exposed outside the mask pattern 8 is etched away, and the W layer 106 below the mask pattern 8 is laterally etched only by chemical reaction.

However, lateral etching due to only this chemical reaction is
The side etching Ie of the side surface of the W gate electrode 6 formed by the RIE process is blocked by the tungsten nitride layer 7 formed at the grain boundaries of the columnar crystals 52.
, will be limited to about 500 to 1000 people.

FIG. 1 (see fl) Then, using the resist pattern 9 and the SiO□ mask pattern 8 as masks, selectively ^S"
After ion implantation and removal of the resist pattern 9, an activation heat treatment is performed to form an n+ type SO film thick region 10 and a drain region 1) having a depth of, for example, about 2,000 to 3,000 layers.

As described above, the side etching amount on the side surface of the W gate electrode 6 is small, and the width of the undercut portion 13 formed under the mask pattern 8 is extremely small as shown by the side etching amount e.

Therefore, the opposing ends of the source and drain regions 10 and 1) formed here are not formed apart from the gate lower region 12.

The method according to the present invention is also carried out according to the following steps.

Refer to FIG. 2(a), that is, as in the previous embodiment, a tungsten layer 1 is placed on the substrate to be processed.
After forming 06, a Sing mask layer having the same thickness as in the above example is formed on the tungsten layer 106 and patterned to form a Sing mask pattern 8 corresponding to the gate electrode on the tungsten layer 106. do.

Referring to FIG. 2(b), the substrate was then heated with ammonia gas (N
The surface of the W layer 106 exposed outside the turn 8 and the grain boundaries of the columnar tungsten crystals 52 in the exposed portion are heated for about 20 minutes at a temperature of about 700 to 900°C in , optionally, the thickness is e.g. 10-50
A tungsten (WN) or (W,N) layer 7 having a thickness of about the same thickness as that of a human body is formed.

Referring to FIG. 2(C), the W layer 106 is then
Perform patterning. By this RIE process, the W layer 106 exposed outside the mask pattern 8 is etched away, and the lateral etching due only to the chemical reaction toward the W layer 106 under the mask pattern 8 is performed by etching the W layer 106 under the mask pattern 8. The amount of side etching on the side surface of the W gate electrode 6 formed by the 1'llB process is prevented by the tungsten nitride layer 7 formed invading the grain boundary closest to the end face of the mask pattern 8 in the above-mentioned process. As in the case, the number of people will be reduced to about 500 to 1,000. Therefore, the width of the undercut portion 13 formed under the mask pattern 8 is a very small width similar to the previous embodiment.

Although not shown hereafter, As2 ions were implanted using the Sing mask pattern 8 as a mask in the same manner as in the previous embodiment.

Then, as in FIG. 1(f), an n'-type source region and an n'-type drain region are formed, the opposite ends of which are in contact with the lower gate region.

According to this method, the -N layer 7 is not formed inside (crystal grain boundaries) of the W layer 106 constituting the gate electrode 6, so a W gate electrode with lower resistance can be obtained compared to the above embodiment. .

〔Effect of the invention〕

As explained above, according to the present invention, in the patterning step when forming the W gate electrode, the amount of reduction in the gate electrode width due to side etching can be suppressed to a minimum, so that the gate electrode width (gate length) Variations in device characteristics due to fluctuations in .

Therefore, the present invention is extremely effective in forming semiconductor devices with high integration and miniaturized elements.

[Brief explanation of the drawing]

Figures 1+al to (f) are process cross-sectional views of one embodiment of the method of the present invention, Figures 2 (al to (C) are process cross-sectional views of another embodiment of the method of the present invention, and Figure 3 is a process cross-sectional view of another embodiment of the method of the present invention. Schematic diagram showing the crystal structure of the tungsten layer Figure 41
8) to (C) are process cross-sectional views of the conventional method. In the figure, ■ is a p-type Si substrate, 2 is a field oxide film, 3 is a p-type channel stopper, 4 is an element formation region, 5 is a gate oxide film, 6 is a W gate electrode, 7 is a tungsten nitride layer, 8 is 5i02 Mask pattern, 9 is resist pattern, IO is n+ type source region, 1) is n" type drain region, 12 is gate lower region, 13 is undercaft part, 52 is columnar W crystal, 106 is W layer, ios is SiO□ The mask layer is shown.

Claims (3)

[Claims] (1) In a method for manufacturing an MIS type semiconductor device having a tungsten gate, when forming a tungsten gate electrode, a gate insulating film is formed on a semiconductor substrate, a tungsten layer is formed on the gate insulating film, and the tungsten layer A method for manufacturing an MIS type semiconductor device, comprising the steps of thermally nitriding the tungsten layer in an ammonia gas, and then patterning the tungsten layer by reactive ion etching treatment using a fluorine-based gas. (2) When thermally nitriding and patterning the tungsten layer, after thermally nitriding the tungsten layer in ammonia gas, an insulating film pattern corresponding to the gate electrode pattern is formed on the tungsten layer, and a reactive ion etching process is performed. A method for manufacturing an MIS type semiconductor device according to claim 1, comprising the steps of: (3) When thermally nitriding and patterning the tungsten layer, a step of forming an insulating film pattern corresponding to the gate electrode pattern on the tungsten layer, thermally nitriding the tungsten layer, and then performing a reactive ion etching process is performed. A method for manufacturing an MIS type semiconductor device according to claim 1, characterized in that: