JPH01174144A - Terminal identifier management circuit - Google Patents

Abstract

PURPOSE:To facilitate the storage of plural TEI values and management of the TEI values by making a memory address correspondent to a terminal identifier TEI value. CONSTITUTION:A terminal equipment writes, e.g., 1 to the address of a memory 2 corresponding to the terminal identifier TEI assigned to itself. Then the TEI of the reception signal is used as an address signal and given to the memory 2, the data of the corresponding address is read and when the read data is 1, it is discriminates that its own equipment is the destination, and when 0, it is discriminated not. On the other hand, in the assignment of the TEI to the terminal equipment at the network side, the TEI is given to the memory as the address signal and 1 is written to a corresponding address. Then whether or not the TEI is assigned is discriminated based on the content of memory, 0 or 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication device that connects a large number of terminals to a network, and more specifically relates to a circuit that manages terminal identifiers that identify terminals.

[Conventional technology]

1 (DLC)
There is known a device that performs communication processing according to a data link layer control procedure of type k Control). 7th
The figure shows the configuration of a home network shown in CCITT Recommendation 1.430, in which a subscriber line 41 such as a telephone line controls a home bus 42, and a control device 43 that terminates the subscriber line is connected. Terminals TEO, TE1, . . . TEn, such as telephones and facsimiles, are connected to the home bus 42.

In the figure, 44.44 is a terminating resistor.

According to the above recommendation, one telephone number corresponds to one control device 43, and a subaddress called a terminal identifier (TEI) is used to distinguish terminals TEO, TEI, . . . TEn. For this reason, it is stipulated that the terminal stores its own TEI value, compares the TEI value of the received signal with its own TEI value, and captures the received signal when the two match.

FIG. 8 shows a terminal identifier management circuit for performing this. 5a is an n-bit register that stores its own TEI value, and this value is stored as Xo...X11-g+X1
l-+, each of these bits is connected to an exclusive NOR gate 5°...5. %-2+511-1. On the other hand, the received n-bit TEI value Y0・
...Y, l-2+Y,, is the NOR gate 5°...
There are 5n-2+5n-1 inputs, and these outputs are input to an n-input ANDNO gate.

5c are these NOR gates 5o-5-2,5,,-+
and AND game b.

As is clear from the configuration of this comparator 5C, the receiving TE
When the I value and the own TEI value stored in the register 5a match, a match output is obtained from the AND game b, which determines that the received signal is addressed to the self, and the TEI value is stored in the register 5a.
The signal sent together with the EI value is taken in, and if they do not match, the signal is ignored.

[Problem that the invention seeks to solve]

According to CCITT Recommendation Q.921, one terminal is allowed to have one or more TEI values. Therefore, in the case of having a plurality of TEI values, a plurality of registers 5a and a plurality of comparators 5C are required, which poses a problem that not only the amount of hardware increases but also the time required for comparison becomes longer.

Also, the TEI value that should be assigned to one terminal depends on its design.
Since it is unknown at the time of manufacturing, there is a problem that rational design cannot be performed.

In addition to this, the network side needs to manage TEI values assigned to all terminals.

The present invention was made in view of the above circumstances, and it is possible to easily store multiple TEI values, compare multiple TEI values at once, and furthermore, regardless of the number of assigned TEI values. The purpose of this invention is to provide a terminal identifier management circuit that can be designed and manufactured for general purposes.

[Means for solving problems]

The terminal identifier management circuit according to the present invention is configured to make memory addresses correspond to TEI values. That is, a memory, means for supplying a terminal identifier to the memory as its address signal, means for writing binary data at an address in the memory corresponding to the address signal supplied by the means, and a means for writing binary data at the address (I! data) at the address. and reading means.

[Effect]

The terminal writes, for example, "1" to the memory address corresponding to the terminal identifier assigned to the terminal. Then, the terminal identifier of the received signal is given to this memory as an address signal, and data at the corresponding address is read out. If the read data is “1”, it can be determined that the device is the destination,
Moreover, if it is "0", it is determined that this is not the case.

On the other hand, on the network side, when allocating a terminal identifier to a terminal, the identifier is given to this memory as an address signal and, for example, "1" is written in the corresponding address. By reading this memory, it can be determined whether the terminal identifier has been allocated or not. If it is "1", it is determined that it has been allocated, and if it is "0", it is determined that it has not been allocated.

〔Example〕

The present invention will be described in detail below based on drawings showing embodiments thereof. FIG. 1 is a block diagram showing a schematic configuration of the entire apparatus of the present invention, and FIG. 2 is a block diagram showing main parts of the terminals TEO, TEI, . . . TEn. Figure 1 shows CCITT Recommendation 1
．． 430 shows the configuration of a home network, in which a main device 10 installed at a telephone office or the like is connected via a subscriber line 41 such as a telephone line. The subscriber line 41 controls a home bus 42 and is connected to a control device 43 which is connected to the end of the subscriber line, and the home bus 42 is connected to terminals TEO, TEI, . . . TEn such as telephones and facsimile machines. has been done. In the figure, 44.44 is a terminating resistor.

In FIG. 2, reference numeral 1 denotes a control unit that accesses the memory 2 based on the received signal, and HDLC frame data FD is transmitted from the network side, that is, from the main device 10 to the subscriber line 41,
It is input via the control device 43, the terminating resistor 44, and the home bus 42. This frame data FD has a format as shown in FIG. 3, with a flag F1 indicating the beginning of the data,
It consists of address data AD including a terminal identifier (TEI), a control code section CNTL indicating the nature of the transmitted data, data I to be transmitted, error check data EC5, and a flag F2 indicating the end of data. The control unit 1 supplies data corresponding to the TEI from the address data AD to the memory 2 as an address signal ADR. In addition, the control unit 1 decodes the control code part CNTL, and when writing "1" to the memory 2 accessed by the address signal ADR, writes the write signal WR and "O". If so, release signal R5
, and when reading data from memory 2, the successive signal R
D is output alternatively. Data DT read from memory 2 is given to control section 1 . In addition, if you want to reset the contents of all addresses in memory 2 to “0”, use the clear signal CL.
The configuration is such that R is given to memory 2, and the clear signal CL
R may be provided by a switch provided on the terminal side, or may be provided from the network side.

The control unit 1 determines whether the received data is addressed to itself as described later, and if it is addressed to itself, flags Fl, F2 . Data (2), etc. excluding the control code section CNTL are given to the subsequent circuit inside the terminal.

Next, the operation of the device of the present invention will be described in the fourth section showing the contents of memory 2.
This will be explained based on the diagram. As shown in FIG. 3, the memory 2 is 8.times.8 bits, and the upper 3 bits of the address signal ADR (6 bits) are used as a column address, and the lower 3 bits are used as a row address. Before using this device or terminal, the memory 2 is reset by giving a clear signal CLR. Then, the contents of memory 2 will be as shown in Figure 4(a).
becomes.

Next, a certain TEI will be assigned to the terminal from the network side, but in this case, the frame data FD received from the main device 10 will be the address data AD containing the assigned TEI value, and the transmitted signal will be assigned the TEI value. It includes a control code part CNTL that indicates that there is a control code part CNTL.

Upon receiving this, the control unit l outputs the write signal WR and also outputs the write signal WR.
The EI value is output as the address signal ADR. When the assigned TEI value is 20 (010100), "1" is written in the address of the third column (010) and the fourth row (100) shown in FIG. 4(b). This means that the terminal is assigned a TEI value of "20".

Then, in subsequent communication, normal frame data FD
is received, the control unit 1 extracts the TEI value from the address data AD in the data and outputs the address signal ADI? The output signal is then applied to the memory 2, and the continuous signal RD is also applied. When the received TEI value is "20", the read data DT is "1", and the control unit 1 takes in the received data as being addressed to itself.

On the other hand, if the data is not "20", the address where the stored data is "0" is accessed, so "0" is read out. In this case, the control unit 1 ignores the data as data addressed to another device.

Figure 4 (C1 shows the contents of the memory 2 of the terminal to which multiple TEI values are assigned. In this case, the TEI values are 7 (000111), 35 (100), in addition to the above-mentioned "20".
011) and 57 (111001) are assigned. That is, the first column (000), the eighth row (111), the fifth column (100), the fourth row (011), and the eighth column (111), the second
The data at the address in row (001) is "1". This terminal has a TEI value of 20 in the frame data FD.
．． 7.35.57 is given, the read data DT becomes "1" and is taken in as self-addressed data. Figure 4 (dl is the TEI value of the received data is “7”)
If so, the data at the corresponding address is shown with hatching.

In Fig. 4 fe), the TEI value of the received data is “10” (0
01010), the read data “O” is shown with hatching. In this case, the received data is ignored.

When TEI values are assigned as described above, if any TEI value is to be released, the main device 10 transmits one piece of frame data having the corresponding control code section CNTL and having the TEI value to be released. Upon receiving this, the control unit 1 provides the TEI value to the memory 2 as an address signal ADR, and also provides a release signal RS.

If the TEI value to be released now is 57, then in Figure 4 (f
), the data at the address in the 8th column, 2nd row is “0”.
” will be replaced.

Such a memory is also provided on the main device 10 side. FIG. 5 shows the main parts of the main device 10, which includes a control section 11 and a memo 2. Prior to TEI value assignment, the control unit 11 applies a clear signal CLR to the memory to set all stored contents to "0". Next, select one of the terminals TEO,T
When assigning a TEI value to EI, .

As a result, the data at the address corresponding to the assigned TEI value becomes 1. Now, "0", "1", "2#,"3", "4"..."1" for a single or multiple terminals.
If "o" is assigned as the TEI value, the contents of the memory will be as shown in FIG.

Therefore, when allocating a new TEI value to any terminal, the previously allocated TEI value must not be used.

Therefore, the control unit 11 provides the TEI value to be allocated to the memory as the address signal ADR, and also sends the read signal RD.
is given to the memory 12. As a result, the data DT at the assumed address is read out to the control section 11.

If the read data DT is "0", it can be determined that the TEI value has not been assigned, and conversely, if it is "1", it can be determined that the TEI value has already been assigned.

When releasing an already allocated TEI value, the TEI value is given to the memory 12 as an address signal ADR, and a release signal R5 is given to the memory 12. As a result, the data at the corresponding address is rewritten from "1" to "0", making it a new value that can be assigned.

FIG. 6 is a circuit diagram showing the configuration of memory 2 or 12,
Here, an example is shown in which the total number of TEIs is 16 (=2'), the memory has a configuration of 4 rows and 4 columns, and the address signal ADR has 4 bits.

Two upper and lower bits of address signal ADR are applied to address decoders 21 and 22. The upper 2 bits are (0,
0) (0,l) (1,0) (1,1), each column of 1.2°3.4 is selected and the lower 2 bits (
0,0) (0,1)(1,0) (1,1) The 1st, 2nd and 3rd rows are selected respectively. CIl+
CI2...C44 indicates a memory cell and CrJ(t
, J=1-4) indicates the i-th row and the j-th column. 3L32,3
3.34 is a write/continue circuit provided for each column for write, read, release, and clear. These write/continue output circuits 31, 32, 33, 34 are composed of a combination of logic circuits, and receive a clear signal CLR and a read signal 1? through lines 23, 24, 25, 26, respectively. D, release signal R3
, is given the write signal WR, and the address decoder 2
A selection signal for each column is given from 1 to 1. Further, the read data DT is outputted via the data line 27.

Next, the configuration of the write/continue output circuit 31, etc. will be explained. The output of the address decoding section 21 is AND game 0a.

30b. Is write signal WR Off? gate 30
c.

An inverter 30d is applied to the gate of an N-channel transistor 30e, one end of which is connected to the ground potential.

The release signal R5 is applied to the OR gate 30c, the gate of the N-channel transistor 30f, and the inverter 30g. Successive signal RD is applied to AND gate 30b. The clear signal CLR is applied to the NO gates 3Qi and 30j, the gate of the N-channel transistor 30s, and the inverter 30t via an inverter 30h. .

The output of OR gate 30c is given to AND gate 30a. The output of the inverter 30d is applied to the gate of a P-channel transistor 30h connected in series with the N-channel transistor 30f and located on the power supply side. The output of the inverter 30g is connected in series with the N-channel transistor 30e and is connected to the P-channel transistor 30jl, which is located on the power supply side. is given to the gate. transistor 3
0, the potential at the intermediate node of the series circuit 30f is applied to bit vA30 via a tristate buffer 30m. 30 transistors.

The potential of the intermediate node of the series circuit 30e is applied to the bit line 30q via a tristate buffer 30p.

The outputs of AND gates 30a and 30b are respectively applied to AND gates 301°30j. The output of the AND gate 303 is used as a control signal for the tri-state buffers 30m and 30p, and the output of the AND gate 30j is used as a control signal for the sense amplifier 30r. The sense amplifier 30r outputs binary data corresponding to the levels of the bit lines 30n and 30q to the data line 27 as a read signal.

Inverter 30f output is P channel transistor 30u
is given to the gate. The transistor 30s is interposed between the bit line 30n and the ground potential, and the transistor 30u is interposed between the power supply potential and the bit line 30q.

Next, the operation of this write/read circuit 31 will be explained.

When a control signal is applied, both transistors 303 and 30r become conductive, the bit line 30n becomes low level, the bit line 30q becomes high level, and "0" is written into each memory cell.

When the write signal WR is applied, one output of the AND gate 30a of the column selected by the address decoding section 21 becomes high level, so that the output of the AND gate 30i becomes high level, and the tristate buffer 30m.

30ρ opens. On the other hand, since the transistor 30e is turned on, the bit line 30n is at a high level, and the bit line 30 is turned on.
q becomes low level, and "1" is written into the memory cells of the selected memory row, contrary to the case of the clear signal.

Conversely, when the release signal RS is applied, the tri-state buffers 30m and 30p are similarly opened, but in this case, the transistors 30f and 30A are turned on, so the bit line 30n is turned on.
becomes low level, 30q becomes high level, and "0" is written into the selected memory cell.

Next, when the successive signal RD is given, the A of the selected column is
The output of the ND gate 30b becomes high level, and the output of the AND gate 30j activates the sense amplifier 30r.
The contents of the accessed memory cell are transferred to bit lines 30n, 3.
Read via 0q.

〔Effect of the invention〕

According to the present invention as described above, in a terminal device, the amount of hardware is constant regardless of the amount of TRI allocated, and the time required for comparison is also constant, which is effective for downsizing the device and increasing the speed of operation. . Furthermore, since the amount of TET to be allocated can be determined a posteriori, restrictions on design and manufacturing are greatly eased.

- The present invention has excellent effects such as being able to immediately determine whether a TRI value has already been assigned on the sumo wrestler device side.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing the entire device of the present invention, Figure 2 is a block diagram of its main parts, Figure 3 is a frame data format diagram, Figure 4 is a conceptual diagram showing the contents of the memory, and Figure 5 is the main part. FIG. 6 is a block diagram of the main part of the device, FIG. 6 is a circuit diagram of the memory, FIG. 7 is a block diagram of the conventional device, and FIG. 8 is a block diagram of the main part. 1... Control unit 2... Memory 10... Main device 4
3...Control device TEO, position...TEn...
Terminal device In the figures, the same reference numerals indicate the same or corresponding parts. Agent Masu Oiwa Figure 2 Figure 3 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Scope of Claims] 1. A communication device that identifies a terminal by a terminal identifier, including a memory, means for providing a terminal identifier as an address signal to the memory, and a communication device that corresponds to an address signal given by the means. A terminal identifier management circuit comprising means for writing binary data into an address of a memory and means for reading binary data at the address. 2. In a communication device that identifies a terminal connected to a network using a terminal identifier, each terminal is provided with a memory, a means for resetting the contents of the memory to a first value, and a means provided from the network side. means for providing the terminal identifier to the memory as the address signal and writing a second value to the corresponding address of the memory; A terminal identifier management circuit comprising: means for reading data from an address; and means for determining that a transmitted signal is addressed to the terminal when the read data is a second value. 3. In a communication device that identifies terminals connected to a network using terminal identifiers, each of the communication devices is provided on the network side and has a memory having a capacity at least equal to the total number of terminal identifiers, and the contents of the memory are set as a first value. means for resetting the terminal; when allocating a terminal identifier to the terminal, the terminal identifier is given to the memory as its address signal; and means for writing a second value to the corresponding address of the memory; and an arbitrary terminal identifier as the address signal. A terminal identifier management circuit comprising means for applying data to the memory and reading data at a corresponding address in the memory.