JPH01177234A - Circuit for managing terminal equipment identifier - Google Patents

Abstract

PURPOSE:To make a quick response to the assignment request of a terminal equipment identifier (TEI) value by storing whether a TEI value is assigned one or unassigned one in a memory and causing a checking procedure actuating signal to be issued when all TEI values become assigned ones. CONSTITUTION:A control section 11 gives a clear signal CLR to a memory 12 so as to set all storing contents of the memory 12 to '0' before TEI value assignment. When the control section 11 assigns a TEI value to one of terminal equipment TE0-TEn, the section 11 gives the TEI value to the memory 12 as an address signal ADR and, at the same time, gives a write signal WR to the memory 12. As a result, the data of the address corresponding to the assigned TEI value become '1'. Therefore, whether the terminal equipment identifier is assigned or unassigned can be discriminated when the memory 12 is read out in such a way that if the read-out result is '1' the TEI value is assigned and if the result is '0' the TEI value is not assigned. When all addresses become '1', namely, when all TEI values are assigned, a checking procedure actuating signal is issued. Therefore, the data processing speed can be increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication device that connects a large number of terminals to a network, and more specifically relates to a circuit that manages terminal identifiers that identify terminals.

[Conventional technology]

HDLC (High-1 level) Link
There is known a device that performs communication processing according to a data link layer control procedure of the control type. FIG. 12 shows the configuration of the home network shown in CCITT Recommendation 1.430, in which a subscriber line 41 such as a telephone line controls a home bus 42, and a control device 43 that terminates the subscriber line 41 is connected. Terminals TEO, TEI, . In the figure, 44.44 is a terminating resistor.

According to the above recommendation, one telephone number corresponds to one control device 43, and a subaddress called a terminal identifier (TEI) is used to distinguish terminals TEO, TEI, . . . TEn. Therefore, prior to communication, the terminal device sends and receives signals to determine the TEI value with the network side,
They are supposed to secure their own TEI value. On the other hand, the terminal may release its own TEI value when the communication ends.

On the other hand, on the network side, whenever a terminal requests TEI allocation, an unused TEI is given to the terminal, but the TEI is usually not released even after communication ends.

According to the above recommendation, the maximum number of terminals is 8, and the maximum TEI value is 1.
There are 28 pieces. On the network side, as mentioned above, -
Since the network does not release the once-used TEI value even after the communication ends, if the number of communications overlaps, there may be no TEI value to be allocated to the terminal.

Therefore, when this state occurs, the network side activates a TEI check procedure to detect whether a TEI is in use or not, releases unused TEI values, and prepares for the next TEI allocation request.

[Problems to be Solved by the Invention] Conventionally, the above-mentioned release processing has been performed by software, but when the processing speed is slow and there are no unused TEI values, the present invention uses a bus in the system to perform the software processing. Karu'&
The purpose of this invention is to provide a terminal identifier management circuit that can speed up data processing by obtaining a TRI check procedure activation signal using hardware.

[Means to solve the problem]

The terminal identifier management circuit according to the present invention associates a memory address with a TEI value, and sets an unallocated TEI value and an already allocated TEI value.
Different data is written depending on the EI value, and a TEI value check procedure activation signal is issued when all addresses have already been allocated data.

[Effect]

On the other hand, when assigning a terminal identifier to a terminal on the network side, the terminal identifier is given to this memory as an address signal and, for example, "1" is written in the corresponding address. By reading this memory, it is possible to determine whether the terminal identifier has been assigned or not. If it is "1", it is determined that the terminal identifier has been assigned, and if it is "O", it is determined that it has not been assigned.

When all addresses become 11", that is, all TE
A check procedure activation signal is issued when the I value is already assigned.

〔Example〕

The present invention will be described in detail below based on drawings showing embodiments thereof. FIG. 1 is a block diagram showing a schematic configuration of the entire apparatus of the present invention, and FIG. 2 is a block diagram showing main parts of the terminals TEO, TEI, . . . TEn. Figure 1 shows CCITT Recommendation 1
．． 430 shows the configuration of a home network, in which a main device 10 installed at a telephone office or the like is connected via a subscriber line 41 such as a telephone line. The subscriber line 41 controls a home bus 42 and is connected to a control device 43 which is connected to the end of the subscriber line, and the home bus 42 is connected to terminals TEO, TEI, . . . TEn such as telephones and facsimile machines. has been done. In the figure, 44.44 is a terminating resistor.

In FIG. 2, reference numeral 1 denotes a control unit that accesses the memory 2 based on the received signal, and is a controller that accesses the HDLC frame data F
D is the network side, that is, from the main device 10 to the subscriber line 4
1, input via the control device 43, terminating resistor 44, and home bus 42. This frame data FD has a format as shown in FIG.
1. Address data AD including a terminal identifier (TEI);
It consists of a control code section CNTL representing the nature of the transmission data, data I to be transmitted, error check data EC5, and a flag F2 representing the end of data. The control unit 1 transfers data corresponding to the TEI from the address data AD to the memory 2 as address data 401? give as. Further, the control unit 1 decodes the control code part CNTL and outputs the address signal ADH.
When writing "1" to memo +72 accessed by , write signal -R, when writing "O", release signal R5, and when reading data from memory 2. selectively outputs the successive signal RD. Data OT read from memory 2 is given to control section l. Also memory 2
When resetting the contents of all addresses to "0", the configuration is such that a clear signal CLR is given to the memory 2, and the clear signal CLR can be given by a switch installed on the terminal side or from the network side. You can also use it as

The control unit 1 determines whether the received data is addressed to itself as described later, and if it is addressed to itself, flags Fl, F2 . Data I, etc. excluding the control code part CNTL are given to the subsequent circuit inside the terminal.

Next, the operation of the device of the present invention will be described in the fourth section showing the contents of memory 2.
This will be explained based on the diagram. As shown in FIG. 3, the memory 2 is 8.times.8 bits, and the upper 3 bits of the address signal ADR (6 bits) are used as a column address, and the lower 3 bits are used as a row address. Before using this device or terminal, the memory 2 is reset by giving a clear signal CLR. Then, the contents of memory 2 will be all 0 as shown in Figure 4(a).
becomes.

Next, a certain TEI will be assigned to the terminal from the network side, but in this case, the frame data FD received from the main device 10 will be the address data AD containing the assigned TEI value, and the transmitted signal will be assigned the TEI value. It includes a control code part CNTL that indicates that there is a control code part CNTL.

Upon receiving this, the control unit 1 outputs a write signal -R and also outputs a write signal -R.
The EI value is output as the address signal ADR. If the assigned TEI value is 20 (010100), 1'' is written to the address in the third column (010) and fourth row (100) shown in FIG. 4(b).This causes the terminal to This means that a TEI value of "20" has been assigned.

Then, in subsequent communication, normal frame data FD
When the address data AD is received, the control unit 1 extracts the TEI value from the address data AD in the data and supplies it to the memory 2 as the address signal ADH, and also gives the continuation signal RD. When the received TEI value is “20”, the read data DT is “
1'', and the control unit 1 takes in the received data as being addressed to itself.

On the other hand, if it is not “20”, the stored data is “0”
Since a certain address is accessed, "0" is read. In this case, the control unit 1 ignores the data as data addressed to another device.

FIG. 4C shows the contents of the memory 2 of the terminal to which a plurality of TEI values are assigned. In this case, the TEI value is 7 (000111), 35 (100) in addition to the above-mentioned “20”.
011) and 57 (111001) are assigned. That is, 1st column (000), 8th row (111), 5th column (
100) The data at the address in the fourth row (011), the eighth column (111), and the second row (001) is "1".

This terminal has a TEI value of 20.
7.35.57, the read data DT becomes "1" and is taken in as self-destination data. FIG. 4(d) shows data at the corresponding address with hatching when the TEI value of the received data is "7".

Figure 4(e) shows that the TEI value of the received data is “10” (0
01010), the read data "0" is shown with hatching. In this case, the received data is ignored.

When TEI values are assigned as described above, if any TEI value is to be released, the main device 10 transmits frame data FD having the corresponding control code section CNTL and having the TEI value to be released. Upon receiving this, the control unit 1 provides the TEI value to the memory 2 as an address signal ADR, and also provides a release signal Rs.

If the TEI value to be released now is 57, then in Figure 4 (f
), the data at the address in the 8th column, 2nd row is “0”.
” will be replaced.

Such a memory is also provided on the main device 10 side. FIG. 5 shows the main parts of the main device 10, which includes a control section 11 and a memo 2. Prior to TEI value assignment, the control unit 11 applies a clear signal CLR to the memory 12 to set all stored contents to "0". Next, select one of the terminals TEO,
When assigning a TEI value to TEI, .

As a result, the data at the address corresponding to the assigned TEI value becomes 1. Now, "0", "1", '2', 13", "4"..."1" for a single or multiple terminals
If 0'' is assigned as the TEI value, the contents of the memory will be as shown in FIG.

Therefore, when allocating a new TEI value to any terminal, the previously allocated TEI value must not be used.

Therefore, the control unit 11 provides the TEI value to be allocated to the memory 12 as the address signal ADR, and also sends the read signal R.
D is given to the memory 12. As a result, data DT at the corresponding address is read to the control section 11.

If the successive data DT is "O", it can be determined that the TEI value has not been assigned, and conversely, if the successive data DT is "O", it can be determined that the TEI value has already been assigned.

When releasing an already allocated TEI value, the TEI value is given to the memory 2 as an address signal ADR, and a release signal R5 is given to the memory 2. As a result, the data at the corresponding address is rewritten from "BI" to "0", making it a new value that can be assigned.

FIG. 6 is a circuit diagram showing the configuration of the memory 2. Here, an example is shown in which the total number of TErs is 16 (=2'), and the memory has a configuration of 4 rows and 4 columns, Address signal ADR has 4 bits.

Two upper and lower bits of address signal ADR are applied to address decoders 21 and 22 respectively. The top 2 focuses are (0,
0) (0, 1) (1, 0) (1, 1), the 1st, 2nd, 3.4th columns are selected, and the lower 2 bits (0, 0
) (0,1)(1,0)(LL)
．． Rows 2, 3, and 4 are selected. Cz, C+□...
C44 indicates a memory cell Ci, and (i, j=1 to 4) indicates the cell in the i row and j column. 3L 32, 33, and 34 are write and continuation circuits for each column provided for write, read, release, and clear. These writing and successive output circuits 31 and 32
, 33 and 34 are composed of a combination of logic circuits, and are supplied with a clear signal CLR, a read signal RD, a release signal R5, and a write signal WR through lines 23, 24, 25, and 26, respectively. A selection signal for each column is provided from the decoding section 21. Further, read data DT is outputted via the data line 27.

Next, the configuration of the write/continue output circuit 31, etc. will be explained. The output of the address decoding section 21 is an AND gate 30a.

30b. Write signal WR is sent to OR gate 30c
, an inverter 30d, and the gate of an N-channel transistor 30e, one end of which is connected to the ground potential.

The release signal RS is applied to the OR gate 30c, the gate of the N-channel transistor 30f, and the inverter 30g. Read signal RD is applied to AND gate 30b. The clear signal CLR is applied to the AND gate 301130J, the gate of the N-channel transistor 30s, and the inverter 30t via the impark 30h.

The output of OR gate 30c is given to AND gate 30a. The output of the inverter 30d is applied to the gate of a P-channel transistor 30h connected in series with the N-channel transistor 30f and located on the power supply side. The output of the inverter 30g is connected in series with the N-channel transistor 30e and is located on the power supply side, the P-channel transistor 30I! , given to the gate. transistor 3
0, the potential of the intermediate node of the series circuit of 30f is applied to the bit line 30n via the tristate buffer 30m. Transistor 30! ! ,.

The potential of the intermediate node of the series circuit 30e is applied to the bit line 30q via a tristate buffer 30p.

The outputs of the ND gates 30a and 30b are applied to AND gates 301 and 303, respectively. The output of the AND gate 301 is used as a control signal for the tri-state buffers 30m and 30p, and the output of the AND gate 30j is used as the control signal for the sense amplifier 30.
r control signal. The sense amplifier 30r outputs binary data corresponding to the levels of the bit lines 30n and 30q to the data line 27 as a read signal.

Inverter 30f output is P channel transistor 30u
is given to the gate. The transistor 30s is interposed between the bit line 30n and the ground potential, and the transistor 30u is interposed between the power supply potential and the bit line 30q.

Next, the operation of this write/read circuit 31 will be explained.

When a control signal is applied, the transistor 30S.

30r are both conductive, bit line 30n is low level, 3
0q becomes high level, and "O" is written into each memory cell.

When the write signal WR is applied, one output of the AND gate 30a of the column selected by the address decoding section 21 becomes high level, so the output of the AND gate 301 becomes high level, and the tristate buffer 730m.

30p opens. On the other hand, since the transistor 30e is turned on, the bit line 30n is at a high level, and the bit line 30 is turned on.
q becomes low level, and 1'' is written into the memory cells of the selected memory row, contrary to the case of the clear signal.

Conversely, when the release signal RS is applied, the tri-state buffers 30m and 30p similarly open, but in this case, the transistors 30f and 30I! , turns on, so bit line 3
When 0n is at low level and 30q is at high level, "0" is written into the selected memory cell.

Next, when the successive signal RD is given, the A of the selected column is
The output of the ND gate 30b becomes high level, and the output of the AND gate 30j activates the sense amplifier 30r.
The contents of the accessed memory cell are transferred to the bit line 30n,
30q.

FIG. 7 shows the configuration of the memory 12, and shows a case where the total number of TEIs is 16 (=2'), similar to the memory 2 in FIG.

The memory cells are denoted by CIl+ C12...C44,
Address decoding section 51 which provides address signal ADR.
Reference numeral 52 is similar to the address decoding sections 21 and 22 shown in FIG. 6, and each bit of the 4-bit binary number of the address signal ADR is represented by TEIo to TEIs. The lower bits TEIo and TEI+ are decoded by the address decoding section 51, and the bit lines b l+ of the four memory cell columns are decoded by the address decoding section 51.
Wl+ b 2+”F; Z+ b 3+ lower 3 and
A signal is issued to lr4, and the upper bit TEIz,
TEI:l is decoded by the address decoding unit 52 and word lines W+, W2, W3 of four memory cell rows
, Wa.

FIG. 8 shows the configuration of the memory cell for C1l, and the configuration itself is well known.

In this way, the read lines DI,, D, 2...D44 for the data held by the memory cells are connected to the P-channel transistors PII+P12...pa4 and the N-channel transistors N,...I' JI2...N,
One end of the P-channel transistor is connected to the power supply, and the other end is connected to each row of the human power lines St, Sz, and NOR gate G1.
3. Connected to N4. N-channel transistors are connected in series in each row, with one end connected to the other end connected to the input lines s, , s2 . s3. Connected to s4. The output of the NOR gate G1 is used as a check procedure starting signal.

Next, the operation of this memory 12 will be explained. Reset all memory cells by clear signal CLR, write signal WR
The writing of "1" by the release signal R5, the writing of "0" by the release signal R5, and the reading of the held data by the read signal RD are the same as in the memory 2, so their explanation will be omitted.

Therefore, when the data held in all memory cells C, , C, □...C44 becomes "1", that is, when all TET values are in use, four P-channel transistors P I
Parallel circuits such as l+ P I□+ P 13+ P 14 and four N-channel transistors Nll+
NI2+ NI:l+ N consisting of a series circuit such as N14
The output of the AND gate, that is, the data of the input line 31 of the NOR gate G1, etc., all become "θ", and the NOR gate G,
The output becomes "1" and the check procedure activation signal STR is obtained.

If the data held in any memory cell is "0", that is, if there is an unallocated TEI value, the N-channel transistor is turned off and the P-channel transistor is turned on, so the input lines s,, St, N3° Either N4 becomes "1" and the NOR gate output STR becomes "0",
The check procedure activation signal STR cannot be obtained.

FIG. 9 shows another embodiment of the memory 12, and FIG. 10 shows a circuit around the memory cell C11.

Hey),%? I b l+TI+ b 2+h2+
b ff, T3+ b a, ■< and forward line W,,
Wz, w3, w, and each memory cell Cl1l CI
□...The connection with C44 is the same as that shown in FIG.

In this embodiment, the data successive line T5+ 1 r T5+
2...U44 is an N-channel transistor N I
The drains of these transistors are connected to the gates of I I + N I 12...N 144, and the drains of these transistors are collectively connected to the P channel transistor P connected in parallel.
2゜1. It is connected to the source of P2゜2, and is also connected to the transistor N l l I + N I +□...N, .

The sources of are collectively connected to the drain of the transistor N2°0. Transistor N2°. Its source is grounded, and its gate is supplied with a precharge signal PRC. Transistor P2°. The drain of +P2.1 is connected to a power supply, and the gate of transistor P2.0 is supplied with a precharge signal PRC.

A NOT gate G2 is interposed between the source and gate of the transistor P2゜1, and the output of this NOT gate G2 is NO.
The T gate G3 manual binding NOT game) 03 output is used as the check procedure activation signal STR. In this circuit, the transistor N l l l + N I +□...N144
and transistor N2°. +P2°. This makes it a precharge type NOR.

When the data held in all memory cells becomes 1", the complementary data is read out. The outputs of the read lines [11, etc.] all become "
0'', so all transistors N + + r +
N I+ z...N, 4. is off and NOT game)
A check procedure activation signal STR is obtained from G3.

In the above embodiment, a static NAND type (Fig. 7) and a precharge NOR type (Fig. 9) were shown.
Static NOR type, precharge NAND type,
Furthermore, it can also be configured as a load type using a P-channel transistor.

In the above embodiment, the 16 memory cells are arranged in a 4×4 arrangement, but it goes without saying that other arrangements such as 2×8 may be used.

Furthermore, in the above-mentioned embodiment, the TEI management in the terminal was performed by the memory 2 similar to the memo 2 on the main device 10 side, but as shown in FIG.
The configuration may be such that the value is stored and compared with the transmitted TEI value using the comparator 5C. That is, 5a is an n-bit register that stores its own TEI value, and this value is stored as Xo...X, 2 . X.

Then, each of these bits is an exclusive NOR
It is given to the gates 5°...5n-2, 5□.

On the other hand, the received n-bit TEI value Y. ...Yn-Z+
Yn-1 is the NOR gate 5°...5fi-z, 5
□1 extraction input, and these outputs are A of n inputs.
The signal is input to the ND gate 5b.

5c are these NOR gates 5. -5.2,5. , and an AND gate 5b.

As is clear from the configuration of this comparator 5c, the receiving TE
When the I value and the own TEI value stored in the register 5a match, a match output is obtained from the AND game 5b, which determines that the received signal is addressed to the self, and the TEI value is stored in the register 5a.
The signal sent together with the EI value is taken in, and if they do not match, the signal is ignored.

Even in such a management circuit on the terminal side, the TEI value stored in the register 5a may be stored in the memory 12 on the main device side.

〔Effect of the invention〕

In the case of the circuit of the present invention as described above, whether the TEI value is unassigned or assigned is stored in the memory, and when all the TE and I values are assigned, the check procedure activation signal is activated. Since the TEI value allocation request is issued, the effect of quickly responding to the TEI value allocation request is achieved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a schematic configuration of the entire device of the present invention;
Fig. 2 is a block diagram showing the main parts of the terminal, Fig. 3 is a frame data format diagram, Fig. 4 is a conceptual diagram showing the contents of the memory, and Fig. 5 is a block diagram showing the main parts of the main device.
Figure 6.7.9 is a circuit diagram around the memory, Figure 8.10 is a circuit diagram of a memory cell, Figure 11 is a circuit diagram showing the configuration of a terminal, and Figure 12 is a circuit diagram showing the configuration of a home network. It is a diagram. 10... Main device 11... Control section 12... Memory 51.52... Address decoding section Pll+ P 12... P44+ Nll+
N12...N44...Transistor G,...
NOR gate Nz++Nzz...NI44 +
N.Z. . , P2°. . P2゜1...transistor In the drawings, the same reference numerals indicate the same or corresponding parts. Agent Masu Oiwa Figure 2 Figure 3 Figure 12 Memory Figure 5 b + 'b-'i recommendation Figure 8 Figure 10 Figure 11 Figure 1, Indication of the case Tokuhan Sho. 3-1495 No. 29
Name of the invention Terminal identifier management circuit 3, relationship to the amended person case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4, Attorney Address: 2-2-3 Marunouchi, Chiyoda-ku, Tokyo (
Contact 03 (213) 3421 Permits Department) ゛Pa:, y
Pa+j2 ゛YoyaR \-- 5, "Detailed Description of the Invention" column of the specification subject to amendment and drawing 6, Contents of the amendment 6-1 "Detailed Description of the Invention" column of the specification (1 ) On page 3, line 20 of the specification, "M) ?HJ" is replaced with "restriction".
I am corrected. (2) Replace rEC3J on page 6, line 4 of the specification with rF.
Correct as csJ. (3) On page 7, line 19 of the specification, replace “4th line” with “
5th line”. 6-2 Figure 3 is corrected as shown in the attached drawing. 7. List of attached documents

Claims (1)

[Claims] 1. In a communication device that identifies terminals connected to a network by terminal identifiers, each of the communication devices is provided on the network side and has a memory having a capacity at least equal to the total number of terminal identifiers, and the contents of the memory are set as a first value. means for resetting, means for assigning a terminal identifier to a terminal device by giving the terminal identifier to the memory as an address signal thereof, and writing a second value to a corresponding address in the memory; What is claimed is: 1. A terminal identifier management circuit comprising: means for detecting that a terminal identifier has been detected; and means for issuing a terminal identifier check procedure starting signal when detecting this.