JPH01173748A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH01173748A JPH01173748A JP62332081A JP33208187A JPH01173748A JP H01173748 A JPH01173748 A JP H01173748A JP 62332081 A JP62332081 A JP 62332081A JP 33208187 A JP33208187 A JP 33208187A JP H01173748 A JPH01173748 A JP H01173748A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- transistors
- oxide film
- transistor
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract description 5
- 230000015556 catabolic process Effects 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 16
- 229910052710 silicon Inorganic materials 0.000 abstract description 16
- 239000010703 silicon Substances 0.000 abstract description 16
- 239000010410 layer Substances 0.000 abstract description 7
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 229920005591 polysilicon Polymers 0.000 abstract description 4
- 239000011229 interlayer Substances 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000009792 diffusion process Methods 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 230000000694 effects Effects 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は同−集積回路内のＭＩＳ トランジスタのゲー
ト絶縁膜厚をそのトランジスタに要求される耐圧に応じ
て変えた半導体集積回路装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit device in which the gate insulating film thickness of a MIS transistor in the integrated circuit is varied depending on the withstand voltage required of the transistor.
従来の技術
近年、電子回路システムの小型化、低コスト化のために
いくつかの集積回路および個別素子で組んだ集積回路の
周辺回路からなる電子回路をワンチップ化した高機能集
積回路が利用さ扛るようになってきた。例えば、その一
つに高電圧を必要とする表示装置を直接駆動するために
高耐圧ＭＩＳトランジスタを内蔵した高耐圧集積回路が
ある。Background of the Invention In recent years, high-performance integrated circuits have been used to reduce the size and cost of electronic circuit systems, in which electronic circuits consisting of several integrated circuits and peripheral circuits of integrated circuits assembled from individual elements are integrated into one chip. I've started to get carried away. For example, one of them is a high voltage integrated circuit that includes a built-in high voltage MIS transistor to directly drive a display device that requires high voltage.
以下に従来のシリコン高耐圧集積回路について説明する
。A conventional silicon high voltage integrated circuit will be explained below.
第２図は従来のシリコン高耐圧集積回路の要部を示す断
面図であり、１は通常のＮチャンネルＭＯ８トランジス
タ、２はＮチャンネル高耐圧ＭＯＳトランジスタ、３は
ｐ型シリコン基板、４はフィールド酸化膜、６はｐ十チ
ャンネルストッパ、６はソースとなるＮ十拡散領域、７
はドレインとなるＮ 拡散領域、８は高耐圧ＭＯＳトラ
ンジスタのオフセット構造を形成しているＮ−拡散領域
、９は均一な厚みとされたゲート酸化膜、１゜はゲート
電極となるポリシリコン導に層、１１は眉間絶縁膜、そ
して１２はアルミ配線層である。FIG. 2 is a cross-sectional view showing the main parts of a conventional silicon high-voltage integrated circuit, in which 1 is a normal N-channel MO8 transistor, 2 is an N-channel high-voltage MOS transistor, 3 is a p-type silicon substrate, and 4 is a field oxidized 6 is a p channel stopper, 6 is an N diffusion region which becomes a source, and 7 is a film.
is an N diffusion region that will become the drain, 8 is an N- diffusion region that forms the offset structure of the high voltage MOS transistor, 9 is a gate oxide film with a uniform thickness, and 1° is a polysilicon conductor that will be the gate electrode. 11 is a glabellar insulating film, and 12 is an aluminum wiring layer.
発明が解決しようとする問題点
集積回路のパターンを微細化して高速化する場合、ゲー
ト長を短かくし、またゲート幅を狭くするとともにゲー
ト酸化膜厚を薄くしなければならないが、ゲート酸化膜
厚を薄くするとトランジスタのドレイン耐圧が下がると
いう問題がある。従って、第２図に示すように単一のゲ
ート酸化膜を用いて形成さｎた従来の構造では、パター
ンの微細化をはかると、他のトランジスタよりも高い耐
圧が要求されるトランジスタの耐圧が低下するという問
題点を有していた。Problems to be Solved by the Invention When miniaturizing integrated circuit patterns to increase speed, it is necessary to shorten the gate length, narrow the gate width, and reduce the gate oxide film thickness. There is a problem that if the transistor is made thinner, the drain breakdown voltage of the transistor decreases. Therefore, in the conventional structure formed using a single gate oxide film as shown in Figure 2, when the pattern is made finer, the breakdown voltage of the transistor, which is required to have a higher breakdown voltage than other transistors, increases. However, there was a problem in that it decreased.
本発明は上記の問題点を解決するもので、高速性が要求
されるトランジスタと高い耐圧が要求さｎるトランジス
タのそｎぞれの特徴を十分に引き出すことができる半導
体集積回路装置の提供を目的とする。The present invention solves the above-mentioned problems, and aims to provide a semiconductor integrated circuit device that can fully bring out the characteristics of transistors that require high speed and transistors that require high breakdown voltage. purpose.
問題点を解決するための手段
この目的を達成するために本発明の半導体集積回路装置
は、高い耐圧が要求さｎるトランジスタのゲート絶縁膜
を高速性が要求さｎるトランジスタのゲート絶縁膜より
も厚くした構成を有している。Means for Solving the Problems In order to achieve this object, the semiconductor integrated circuit device of the present invention has a structure in which the gate insulating film of a transistor that requires a high breakdown voltage is made smaller than the gate insulating film of a transistor that requires high speed performance. It also has a thicker structure.
作用
この構成によれば、高速性の要求さｎるトランジスタよ
りもゲート絶縁膜を厚くしたトランジスタはそのドレイ
ン接合の電界強度の減少によって高耐圧化されるため、
それぞれのトランジスタの特徴を十分に引き出す最適な
設計を行うことができる。Effects According to this configuration, a transistor with a thicker gate insulating film than a transistor that requires high speed has a higher withstand voltage due to a reduction in the electric field strength at its drain junction.
It is possible to perform an optimal design that fully brings out the characteristics of each transistor.
実施例
以下本発明の一実施例について、図面を参照しながら説
明する。EXAMPLE An example of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例におけるシリコン高耐圧集積
回路の要部を示す断面を示すものである。FIG. 1 shows a cross section showing the main parts of a silicon high voltage integrated circuit according to an embodiment of the present invention.
第１図において、１３は薄いゲート酸化膜、１４はゲー
ト酸化膜１３よりも厚いゲート酸化膜である。なお１は
ＮチャンネルＭＯＳトランジスタ、２はＮチャンネル高
耐圧ＭＯＳトランジスタ、３はｐ型シリコン基板、４は
フィールド酸化膜、６はｐ十チャンネルストッパ、６．
了はＨ十拡散領域、８はＮ−拡散領域、１ｏはポリシリ
コン導電層、１１は層間絶縁膜、そして１２はアルミ配
線層であり、こｎらは従来例の構成と同じものである。In FIG. 1, 13 is a thin gate oxide film, and 14 is a gate oxide film thicker than gate oxide film 13. Note that 1 is an N-channel MOS transistor, 2 is an N-channel high voltage MOS transistor, 3 is a p-type silicon substrate, 4 is a field oxide film, 6 is a p+ channel stopper, 6.
8 is a H diffusion region, 8 is an N- diffusion region, 1o is a polysilicon conductive layer, 11 is an interlayer insulating film, and 12 is an aluminum wiring layer, which are the same as the conventional example.
上記の構成のシリコン高耐圧集積回路の製作にあたり、
膜厚が異る２種類のゲート酸化膜１２と１３は第３図で
示す過程を経て形成さ扛る。先ず第３図ａに示すように
フィールド酸化膜１０２及びチャンネルストッパ１０３
の形成さｎたシリコン基板１０１を熱酸化して２５０ム
程度の薄い酸化シリコン膜１０４を作り、次に第３図す
に示すように高耐圧ＭＯＳトランジスタを形成する部分
上をレジスト１０６で覆い通常のＭＯＳトランジスタを
形成する部分の薄い酸化シリコン膜１０４をエツチング
して除去する。次いで、第３図Ｃに示すようにレジスト
を除去した後熱酸化を行い、通常のＭＯＳトランジスタ
を形成する部分に２００〜３００ム程度の薄い酸化シリ
コン膜１０６を形成する。この過程で高耐圧ＭＯＳトラ
ンジスタを形成する部分の酸化膜厚が増し、前者よりも
厚い４００〜６００ム程度の酸化シリコン膜１０了が形
成される。またその他の工程は従来から行われている工
程そのを用いることができる。In manufacturing the silicon high voltage integrated circuit with the above configuration,
Two types of gate oxide films 12 and 13 having different film thicknesses are formed through the process shown in FIG. First, as shown in FIG. 3a, a field oxide film 102 and a channel stopper 103 are formed.
A silicon oxide film 104 having a thickness of about 250 μm is formed by thermally oxidizing the silicon substrate 101 on which the MOS transistors are formed, and then, as shown in FIG. The thin silicon oxide film 104 in the portion where the MOS transistor is to be formed is removed by etching. Next, as shown in FIG. 3C, after removing the resist, thermal oxidation is performed to form a thin silicon oxide film 106 of about 200 to 300 μm in the area where a normal MOS transistor will be formed. In this process, the thickness of the oxide film increases in the portion where the high voltage MOS transistor is to be formed, and a silicon oxide film 10 is formed which is thicker than the former with a thickness of about 400 to 600 μm. In addition, for other steps, conventional steps can be used.
以上のように構成さｎた本実施例のシリコン高耐圧集積
回路では、高耐圧ＭＯＳトランジスタのゲート酸化膜を
通常のＭＯＳトランジスタのゲート酸化膜よりも厚くし
たことにより、高耐圧ＭＯＳトランジスタのドレイン耐
圧をそのオフセット構造による改善以上に高めることが
でき、さらにオフセット構造を形成しているＮ−拡散領
域の幅を狭くすることで同じドレイン耐圧でも占有面積
の小さいトランジスタを裏作することができる。In the silicon high-voltage integrated circuit of this embodiment configured as described above, the gate oxide film of the high-voltage MOS transistor is made thicker than the gate oxide film of a normal MOS transistor, so that the drain breakdown voltage of the high-voltage MOS transistor is increased. By narrowing the width of the N- diffusion region forming the offset structure, it is possible to fabricate a transistor with the same drain breakdown voltage but with a smaller occupied area.
なお、本実施例ではトランジスタをＮチャンネルとした
が、これはＰチャンネルでもよいし、ＮチャンネルとＰ
チャンネルの両方が含１ｎていても良い。また、他のト
ランジスタより高い耐圧の要求さ扛るＭＩＳＩ−ランジ
スタとしてオフセット構造を有した高耐圧ＭＯＳトラン
ジスタを使用したシリコン高耐圧集積回路についてその
実施例を示したが、ダイナミックＲＡＭやマイクロプロ
セッサ−などの５ｖ程度の低電圧で動作するものに使用
してもよい。この場合、内部の回路は５ｖ以下の電圧で
動作し入出力の部分のみゲート絶縁膜を厚くして５ｖで
動作するようにす扛ば、内部の回路のパターンをさらに
微細化することができ、チップ面積の大幅な縮小を実現
することができる。In this embodiment, the transistor is an N-channel transistor, but it may be a P-channel transistor, or an N-channel transistor and a P-channel transistor.
Both channels may be included. In addition, we have shown examples of silicon high-voltage integrated circuits that use high-voltage MOS transistors with an offset structure as MISI transistors, which require a higher breakdown voltage than other transistors, but also apply to dynamic RAM, microprocessors, etc. It may be used for devices that operate at a low voltage of about 5V. In this case, the internal circuit operates at a voltage of 5V or less, and if the gate insulating film is thickened only at the input/output portion so that it operates at 5V, the pattern of the internal circuit can be further miniaturized. A significant reduction in chip area can be achieved.
また、実施例では基板をシリコンとし、ゲート絶縁膜を
酸化シリコン膜としたが、基板がガリウム・ヒ素のよう
な化合物半導体であってもよく、さらに、ゲート絶縁膜
が窒化シリコン膜、酸化タンタル膜、酸化アルミニウム
膜などでもよく、また、そｎらの多層膜であってもよい
。Further, in the embodiment, the substrate is silicon and the gate insulating film is a silicon oxide film, but the substrate may be a compound semiconductor such as gallium arsenide, and the gate insulating film may be a silicon nitride film or a tantalum oxide film. , an aluminum oxide film, or a multilayer film thereof.
発明の効果
本発明は同一の集積回路内に、ゲート絶縁膜厚の異なっ
た２種類以上のＭＩＳ トランジスタを設けたことによ
り、高速性が要求さ扛るトランジスタと高い耐圧が要求
さｎるトランジスタを内蔵する集積回路を実現すること
ができ、そ扛ぞｎのトランジスタの特徴を十分に引き出
すことができる。Effects of the Invention The present invention provides two or more types of MIS transistors with different gate insulating film thicknesses in the same integrated circuit. A built-in integrated circuit can be realized, and the characteristics of the transistor can be fully brought out.
第１図は本発明の一実施例におけるシリコン高耐圧集積
回路の要部を示す断面図、第２図は従来のシリコン高耐
圧集積回路の要部を示す断面図、第３図は本発明の一実
施例における２種類のゲート酸化膜厚を得る方法を説明
するための工程順断面図である。
１・・・・・・ＮチャンネルＭＯ３トランジスタ、２・
・・・・・Ｎチャンネル高耐圧ＭＯＳトランジスタ、３
・・・・・・ｐ型シリコン基板、４・・・・・・フィー
ルド酸化膜、６・・・・・・Ｐ十チャンネルストッパ、
６，７・・・・・・Ｎ＋拡散領域、８・・・・・・Ｎ−
拡散領域、９・・・・・・ゲート酸化膜１．１０・・・
・・・ポリシリコン導電層、１１・・・・・・層間絶縁
膜、１２・・・・・・アルミ配線層、１３・・・・・・
薄いゲート酸化膜、１４・・・・・・厚いゲート酸化膜
、１０１・・・・・・シリコン基板、１０２・・・・・
・フィールド酸化膜、１０３・・・・・・チャンネルス
トッパ、１ｏ４・・・・・・２６０λ程度の薄い酸化シ
リコン膜、１０５・・・・・・レジスト、１０６・・・
・・・３ｏｏＸ程度の薄い酸化シリコン膜、１０７・・
・・・・６００Ｘ程度の酸化シリコン膜。FIG. 1 is a cross-sectional view showing the main parts of a silicon high voltage integrated circuit according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing the main parts of a conventional silicon high voltage integrated circuit, and FIG. 3 is a cross-sectional view showing the main parts of a conventional silicon high voltage integrated circuit. FIG. 3 is a step-by-step cross-sectional view for explaining a method of obtaining two types of gate oxide film thicknesses in one embodiment. 1...N-channel MO3 transistor, 2...
...N-channel high voltage MOS transistor, 3
...P-type silicon substrate, 4 ...field oxide film, 6 ...P channel stopper,
6, 7...N+ diffusion region, 8...N-
Diffusion region, 9...Gate oxide film 1.10...
... Polysilicon conductive layer, 11 ... Interlayer insulating film, 12 ... Aluminum wiring layer, 13 ...
Thin gate oxide film, 14... Thick gate oxide film, 101... Silicon substrate, 102...
・Field oxide film, 103...Channel stopper, 1o4...Thin silicon oxide film of about 260λ, 105...Resist, 106...
...Thin silicon oxide film of about 3ooX, 107...
...Silicon oxide film of about 600X.
Claims (3)
ート電極を有し、さらにゲート絶縁膜厚の異なる２種類
以上のＭＩＳトランジスタを有することを特徴とする半
導体集積回路装置。(1) A semiconductor integrated circuit device characterized by having gate electrodes formed in the same process in the same semiconductor substrate and two or more types of MIS transistors having different gate insulating film thicknesses.
も１種類が他のトランジスタより高い耐圧が要求される
ＭＩＳトランジスタであることを特徴とする特許請求の
範囲第１項記載の半導体集積回路装置。(2) The semiconductor integrated circuit device according to claim 1, wherein at least one type of the two or more types of MIS transistors is a MIS transistor that requires a higher breakdown voltage than the other transistors.
３００Å、厚い方が４００Å〜６００Åであることを特
徴とする特許請求の範囲第１項記載の半導体集積回路装
置。(3) There are two types of gate insulating film thickness, the thinner one is 200 Å ~
2. The semiconductor integrated circuit device according to claim 1, wherein the thickness is 300 Å, and the thicker one is 400 Å to 600 Å.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62332081A JPH01173748A (en) | 1987-12-28 | 1987-12-28 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62332081A JPH01173748A (en) | 1987-12-28 | 1987-12-28 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01173748A true JPH01173748A (en) | 1989-07-10 |
Family
ID=18250934
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62332081A Pending JPH01173748A (en) | 1987-12-28 | 1987-12-28 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01173748A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100955839B1 (en) * | 2007-12-28 | 2010-05-06 | 주식회사 동부하이텍 | Method for forming multi capacitor |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61263261A (en) * | 1985-05-17 | 1986-11-21 | Nec Corp | Manufacture of mos type semiconductor element |
-
1987
- 1987-12-28 JP JP62332081A patent/JPH01173748A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61263261A (en) * | 1985-05-17 | 1986-11-21 | Nec Corp | Manufacture of mos type semiconductor element |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100955839B1 (en) * | 2007-12-28 | 2010-05-06 | 주식회사 동부하이텍 | Method for forming multi capacitor |
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