JPH01171234A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01171234A
JPH01171234A JP62329079A JP32907987A JPH01171234A JP H01171234 A JPH01171234 A JP H01171234A JP 62329079 A JP62329079 A JP 62329079A JP 32907987 A JP32907987 A JP 32907987A JP H01171234 A JPH01171234 A JP H01171234A
Authority
JP
Japan
Prior art keywords
chip
leads
semiconductor chip
close
side faces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62329079A
Other languages
Japanese (ja)
Other versions
JP2565360B2 (en
Inventor
Atsushi Komoro
敦 小師
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Japan Ltd
Original Assignee
Texas Instruments Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Japan Ltd filed Critical Texas Instruments Japan Ltd
Priority to JP62329079A priority Critical patent/JP2565360B2/en
Publication of JPH01171234A publication Critical patent/JPH01171234A/en
Application granted granted Critical
Publication of JP2565360B2 publication Critical patent/JP2565360B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Abstract

PURPOSE:To improve positional accuracy of a semiconductor chip, by close contacting external leads directly with side faces of the semiconductor chip in electrically insulated relation, and electrically connecting the external leads with electrodes on the semiconductor chip. CONSTITUTION:Each external lead 34 whose outer periphery is coated with an insulative material 24 is close contacted directly with a pair of opposing side faces 22, 23 of a semiconductor chip 31 consisting of an active area 20 and a peripheral area 21. While such close contact between the external leads and the semiconductor chip is kept by a special-purpose jig, bonding pads 25 on the chip 31 are wire bonded with the top faces of the leads 34 by means of wires 33. The device as a whole is sealed with resin 35 by the transfer molding process or the like. Since the leads 34 are close contacted with the side faces of the chip 31 in electrically insulated relation and they are connected with each other by wire bonding, there is no clearance between the chip 31 and the leads 34 and the size of the packaging structure is close to the outer diameter of the chip 31. Further, since the leads 34 are contacted directly with the chip side faces, it is possible to ensure satisfactory positional accuracy of the chip 31 in the package.

Description

【発明の詳細な説明】 イ、産東上の利用分野 本発明は半導体装置に関し、特に半導体チップの実装構
造(パンケージング)に関するものである。
DETAILED DESCRIPTION OF THE INVENTION A. Field of Application of Santo The present invention relates to semiconductor devices, and particularly to a mounting structure (pancaging) for semiconductor chips.

口、従来技術 従来のパッケージング技術として一般に、第12図に示
すように、半導体(IC)チップlをリードフレームの
チップマウント部2上に固定し、ボンディングワイヤ3
によってチップ1上のパッドとリードフレームの外部リ
ード4とを電気的に接続し、次に全体をトランスファモ
ールド法によって樹脂5で封止している。
BACKGROUND ART Conventional packaging technology generally involves fixing a semiconductor (IC) chip l on a chip mount part 2 of a lead frame and bonding wires 3 as shown in FIG.
The pads on the chip 1 are electrically connected to the external leads 4 of the lead frame, and then the whole is sealed with resin 5 by transfer molding.

また、他のパンケージング技術としては、第13図のよ
うに、半導体チップIを基板6上に固定し、やはりワイ
ヤ3によってヘッダ7を介して外部リード4に対し半導
体チップlを電気的に接続し、更に上面に絶縁体8を介
して透明窓9を固定した構造が知られている。
In addition, as another pancaging technique, as shown in FIG. However, a structure is known in which a transparent window 9 is further fixed to the upper surface via an insulator 8.

しかしながら、上記したパンケージングにおいてはいず
れも、チップ1をマウントするためにその周囲に十分な
りリアランス10が必要であり、これによってパフケー
ジのサイズ自体が不可避的に大きくなってしまう。しか
も、チップlのマウント位置精度が不十分である場合、
例えばCCD(Charge Coupled Dev
tce)等のように〜パッケージ外形に対してチップ1
の位置精度が厳しく要求されるデバイスでは重大な問題
となる。例えば、内視鏡用(胃や直腸用のカメラ)の小
型CODの場合、少しの位置ずれが生じても、チップ1
が小型であるために、そのずれによる特性変化(例えば
受光面の有効面積又は効率の変動)が顕著に生じる、ま
た、上記位置ずれの結果、ワイヤ3がモールド時の樹脂
圧等によって別のリードに接触してショートやリークの
原因となることもある。
However, in all of the above-described pancages, a sufficient clearance 10 is required around the chip 1 in order to mount the chip 1, which inevitably increases the size of the puff cage itself. Moreover, if the mounting position accuracy of the chip l is insufficient,
For example, CCD (Charge Coupled Dev
tce), etc. ~ chip 1 relative to the package outline
This becomes a serious problem for devices that require strict positional accuracy. For example, in the case of a small COD for endoscopes (stomach and rectal cameras), even if there is a slight positional shift, the tip 1
Because of the small size of the wire 3, characteristic changes (for example, changes in the effective area or efficiency of the light-receiving surface) due to the misalignment occur significantly.As a result of the above-mentioned misalignment, the wire 3 may be connected to another lead due to resin pressure during molding, etc. It may come into contact with the metal and cause a short circuit or leak.

ハ0発明の目的 本発明の目的は、パッケージのサイズを小さくし、かつ
半導体チップの位置精度を向上させた半導体装置を提供
するものである。
OBJECTS OF THE INVENTION An object of the present invention is to provide a semiconductor device in which the size of the package is reduced and the positional accuracy of the semiconductor chip is improved.

二6発明の構成 即ち、本発明は、電気的絶縁状態で外部リードが半導体
チ・ノブの側面に直接密着され、かつ前記外部リードと
前記半導体チップの電極とが電気的に接続されている半
導体装置に係るものである。
26 Structure of the Invention That is, the present invention provides a semiconductor device in which an external lead is directly closely attached to a side surface of a semiconductor chip in an electrically insulated state, and the external lead and the electrode of the semiconductor chip are electrically connected. It is related to the device.

ホ、実施例 以下、本発明の詳細な説明する。E, Example The present invention will be explained in detail below.

第1図〜第3図の例においては、アクティブエリア20
及び周辺エリア21からなる半導体チップ3Iの対向し
た一対の側面22.23に対し、外周面が絶縁物質24
のコーティングされた外部リード34が直接的に密着せ
しめられている。そして、この密着状態を専用の治具(
図示せず)で保持しながら、チップ31のボンディング
パソド25とリード34の上面とがワイヤ33によって
ワイヤボンディングされ、しかる後に全本がトランスフ
ァモールド法で樹脂35 (但し、第1図、第2図では
仮想線で示す。)によって封止される。
In the example of FIGS. 1 to 3, the active area 20
The outer peripheral surface is made of an insulating material 24 with respect to a pair of opposing side surfaces 22 and 23 of the semiconductor chip 3I consisting of a peripheral area 21 and a peripheral area 21.
The coated external leads 34 are directly brought into close contact with each other. This adhesion condition is then checked using a special jig (
The bonding pad 25 of the chip 31 and the upper surface of the leads 34 are wire-bonded with the wire 33 while holding the chip 31 with the resin 35 (not shown). (Indicated by phantom lines in the figure.)

上記において、リード34は、金属ビン26の表面に5
iOz 、Al2203等の無機絶縁体又はポリイミド
等の有機絶゛縁体の薄膜24をコーティングしたものか
らなっている。また、ワイヤ33によるワイヤボンディ
ング及びトランスファモールド自体は従来法によって行
っている。
In the above, the lead 34 is attached to the surface of the metal bottle 26.
It is coated with a thin film 24 of an inorganic insulator such as iOz or Al2203 or an organic insulator such as polyimide. Further, wire bonding using the wire 33 and transfer molding itself are performed by conventional methods.

このように、従来のようなリードフレームを使用せず、
チップ31の側面に対してリード34を電気的絶縁状態
で密着され、かつワイヤボンディングで両者間を接続し
ているので、チップ31とリード34との間には既述し
た如きクリアランスがなくなり、作製されたパフケージ
ング構造はチップ31の外径に近い大きさとなる。
In this way, without using a conventional lead frame,
Since the leads 34 are closely attached to the side surfaces of the chip 31 in an electrically insulating state and are connected by wire bonding, there is no clearance between the chip 31 and the leads 34 as described above, which makes the fabrication process easier. The resulting puff caging structure has a size close to the outer diameter of the tip 31.

また、リード34をチップ側面に直接密着させるため、
パッケージ中のチップ31の位置精度が十分となる。し
かも、位置ずれが生じないために、ワイヤボンディング
を常に確実に行え、ショート不良等を防止することがで
きる。
In addition, in order to bring the leads 34 into direct contact with the side surface of the chip,
The positional accuracy of the chip 31 in the package becomes sufficient. Moreover, since positional deviation does not occur, wire bonding can always be performed reliably, and short-circuit defects and the like can be prevented.

第4図は、他の例によるパッケージを示すものである。FIG. 4 shows a package according to another example.

この例では、チップ31を基板36上に固定し、この基
板36を貫通して外部リード34を下方へ取り出すと共
に、この外部リード34をチップ3Iに密着させてワイ
ヤ33でボンディングしている。
In this example, the chip 31 is fixed on a substrate 36, and the external leads 34 are taken out downwardly by passing through the substrate 36, and the external leads 34 are brought into close contact with the chip 3I and bonded with wires 33.

そして、基板36の周辺部に設けた絶縁体28を介して
上面に透明ガラス窓29を設けている。
A transparent glass window 29 is provided on the upper surface of the substrate 36 via an insulator 28 provided around the periphery thereof.

このパッケージでは、窓29側から光を入射させ、これ
をチ・7プ31で受光させることができる。
In this package, light can enter from the window 29 side and be received by the chip 31.

従って、チップ31として、上記の20が小型CCDの
受光面等に用いる胃又は直腸の内視鏡用の小型CCDを
使用することができる。このような場合、上記した理由
からパ・7ケージサイズの小型化及びチップ位置精度の
向上によって、小型CODにとって極めて有利となる。
Therefore, as the chip 31, it is possible to use the small CCD 20 mentioned above for a stomach or rectal endoscope, which is used as the light receiving surface of the small CCD. In such a case, for the above-mentioned reasons, miniaturization of the package size and improvement of chip position accuracy are extremely advantageous for small-sized CODs.

第5図には、小型CCDを内視鏡に用いた例を示した。FIG. 5 shows an example in which a small CCD is used in an endoscope.

ここで、図中の37はプリント基板又はコネクタ、38
は集束レンズ、3日はフレキシブルチューブ、40は光
源用光ファイバ、41は筒状ソケットを夫々概略的に示
すものである。
Here, 37 in the figure is a printed circuit board or connector, and 38
3 schematically shows a focusing lens, 3 a flexible tube, 40 an optical fiber for a light source, and 41 a cylindrical socket.

次に、第6図及び第7図について、更に他の実施例を説
明する。
Next, still another embodiment will be described with reference to FIGS. 6 and 7.

この例の場合、外部リード34を各列毎に基板36aと
36bとに夫々取り付け、これらの側基板を突き合せて
組み合せると共に、その間にチップ31を挟着した構造
となっている。
In this example, the external leads 34 are attached to the substrates 36a and 36b in each row, and these side substrates are butted and combined, and the chip 31 is sandwiched between them.

従って、第4図の例に比べて、各リード34の位置を予
め最終製品のリードピンチに適合するように決めておけ
る等、各部を予め位置決めしておけるため、チップ31
の固定、ワイヤボンディング等を行い易くなる。しかも
、第4図と同様に、基板上に固定する構造であるから、
パフケージとしての機械的強度が大きくなる。
Therefore, compared to the example shown in FIG.
It becomes easier to perform fixing, wire bonding, etc. Moreover, since it is a structure that is fixed on the board as in Fig. 4,
The mechanical strength of the puff cage is increased.

第8図〜第10図の例は、外部リード34を2重の絶縁
性テープ42−43間に挾み込み、このまま接着剤又は
粘着剤44によってチップ31の周面に巻き付けている
。従って、リード34は絶縁性テープ42−43間にあ
ってチップ31に対して絶縁されているので、上述した
如き絶縁性薄膜24は必要ではなく、金属ピン26を直
接用いることができる。そして、各リード34は予め最
終製品のリードピッチに合せて配しておける。この場合
、テープ42.43の接合面に接着剤又は粘着剤を塗布
しておけば、リードの取り付けは容易となる。そして、
テープ42.43を図示の如くにチップ31の周りに巻
き付け、テープ押え治具(図示せず)によって−時的に
固定した状態で、ワイヤ33によるボンディングを行い
、更に樹脂封止を行う。
In the example shown in FIGS. 8 to 10, the external lead 34 is sandwiched between two layers of insulating tape 42 and 43, and is wrapped around the circumferential surface of the chip 31 with adhesive or adhesive 44. Therefore, since the leads 34 are located between the insulating tapes 42 and 43 and are insulated from the chip 31, the insulating thin film 24 as described above is not necessary, and the metal pins 26 can be used directly. Each lead 34 can be arranged in advance in accordance with the lead pitch of the final product. In this case, if an adhesive or adhesive is applied to the bonding surfaces of the tapes 42 and 43, attachment of the leads will be facilitated. and,
Tapes 42 and 43 are wrapped around the chip 31 as shown, and bonding is performed using the wire 33 while temporarily fixed with a tape holding jig (not shown), followed by resin sealing.

この例の場合は、予めテープ42−43間にリード34
を挟着しておけるので、リードの位置を決めておき易く
、かつテープの巻き付けでチ・ノブ31の周囲に取り付
けるためにその取り付は作業が容易である。
In this example, the lead 34 is placed between the tapes 42 and 43 in advance.
Since the lead can be clamped, it is easy to determine the position of the lead, and since it can be attached around the chi knob 31 by wrapping tape, the installation work is easy.

第8図の例においては、テープ42.43の代りに同サ
イズ(即ち、チップ外形と同サイズ)の絶縁性の枠を用
い、この枠にリード34を挿通して埋め込んでおき、こ
れを加熱して枠を外方へ幾分膨張、拡大させてから、内
側にチップ3.1を挿入し、しかる後に冷却することに
よって枠を元の形に収縮させることができる。即ち、枠
の拡大→収縮によって、チップ31に対するリード34
の固定を連続的な熱プロセスで実現することができるの
で、作業性が向上することになる。そして、その後は上
記したと同様にワイヤボンディング、樹脂封止を行うこ
とができる。
In the example shown in FIG. 8, an insulating frame of the same size (that is, the same size as the chip external shape) is used instead of the tapes 42 and 43, and the leads 34 are inserted and embedded in this frame, and then heated. After the frame is expanded and expanded somewhat outwardly, the chip 3.1 is inserted inside, after which the frame can be contracted back to its original shape by cooling. That is, by expanding the frame and then contracting it, the leads 34 relative to the chip 31 are
can be achieved through a continuous thermal process, improving work efficiency. After that, wire bonding and resin sealing can be performed in the same manner as described above.

第11図の例では、半導体チップ31の側面22.23
に対し、絶縁物質(例えば接着剤)44を介して外部リ
ード34が密着せしめられ、かつり−ド34側に設けた
バンプ電極45をパッド25上に熱圧着して電気的接続
を行っている。そして全体は上述と同様に樹脂封止され
てよい。
In the example of FIG. 11, the side surfaces 22 and 23 of the semiconductor chip 31 are
On the other hand, an external lead 34 is closely attached via an insulating material (for example, adhesive) 44, and a bump electrode 45 provided on the side of the lead 34 is thermocompression bonded onto the pad 25 for electrical connection. . The entire structure may be sealed with resin in the same manner as described above.

以上、本発明の詳細な説明したが、上述の例は本発明の
技術的思想に基いて更に変形可能である。
Although the present invention has been described in detail above, the above-mentioned examples can be further modified based on the technical idea of the present invention.

例えば、チップに対する外部リードの絶縁手段は上述の
コーテイング膜、接着剤、テープ等以外にも種々採用可
能であるし、またそうした絶縁手段はチップ側に設けて
おいてもよい。リードにコーティングする絶縁膜はチッ
プ側だけに存在していてもよい。また、チップとリード
との接続も上述のものに限ることなく、様々な方式で行
うことができる。上述の第4図や第7図の例においても
、第3図に示した如き樹脂封止構造のバ・7ケージに変
形してもよい。第7図の例では更に、リードを取り付け
る基板の個数やサイズ等を変更してよく、例えば3個又
はそれ以上の基板の組み合せでもよい。第11図のバン
プ45はチップ側に形成してもよい。なお、本発明の適
用できるデバイスは、上述のCCDに限ることはなく、
他のIC一般に拡げることができる。
For example, various insulation means for external leads to the chip can be used in addition to the above-mentioned coating film, adhesive, tape, etc., and such insulation means may be provided on the chip side. The insulating film coated on the leads may be present only on the chip side. Further, the connection between the chip and the leads is not limited to the above-mentioned method, and can be made in various ways. The examples shown in FIGS. 4 and 7 described above may also be modified to a resin-sealed structure bar 7 cage as shown in FIG. 3. In the example shown in FIG. 7, the number and size of the boards to which the leads are attached may be changed; for example, three or more boards may be combined. The bumps 45 shown in FIG. 11 may be formed on the chip side. Note that the devices to which the present invention can be applied are not limited to the above-mentioned CCD,
It can be extended to other ICs in general.

へ0発明の作用効果 本発明は上述の如く、外部リードが電気的絶縁状態で半
導体チップの側面に直接密着され、かつ両者間の電気的
に接続されるようにしているので、チップとリードとの
間にはクリアランスがな(なり、作製されたパンケージ
ング構造はチップの外径に近い大きさとなる。
Effects of the Invention As described above, in the present invention, the external leads are directly adhered to the side surfaces of the semiconductor chip in an electrically insulated state, and the electrical connection between the two is made. There is no clearance between them, and the fabricated pancaging structure has a size close to the outer diameter of the chip.

また、リードをチップ側面に直接密着させるため、パン
ケージ中のチップの位置精度が十分となる。
Furthermore, since the leads are brought into direct contact with the side surfaces of the chip, the positioning accuracy of the chip in the pancage is sufficient.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はパッケージの斜視図、 第2図は第1図の平面図、 第3図は第2図のu−m線に沿う断面図、第4図は他の
例によるパッケージの断面図、第5図は内視鏡用として
用いる例の要部概略断面図、 第6図は他の例によるリード及びリード固定用の基板を
左右分離して示す斜視図、 第7図は第6図の基板を用いたパッケージの断面図、 第8図は他の例によるパッケージの斜視図、第9図はテ
ープに取り付けられたリードの一部分の正面図、 第1O図は第9図の平面図、 第11図は更に他の例によるパッケージの断面図 である。 第12図、第13図は従来のパッケージの各断面図であ
る。 なお、図面に示す符号において、 20−−−−−−−−−−−−−アクティブエリア21
−−−−−−−−−−−周辺エリア22.23−・−一
一−−−−側面 24−−−・−・−絶縁性薄膜 25−−−−−−−−−−−−パッド 26−−−−−−−−・−・−金属ピン28.44−−
−−−−−・−絶縁物質29−−−−−−−−一透明窓 31−−−−−−−−−−−−一半導体チツブ33−−
−−−−−−−−ワイヤ 34−−−−−−−−−−−外部リード35−−−−−
−−−−−−一樹脂 36.36a、36 b−−−−−−−−一基板42.
43−・−−−−一−−−テープ44−−−−−−−−
−・−接着剤又は粘着剤45−・−・−・・−バンブ電
極 である。 代理人  弁理士  逢 坂   宏 第1図 第2図 第3図 第4図 第9図 第10図 第11図
FIG. 1 is a perspective view of the package, FIG. 2 is a plan view of FIG. 1, FIG. 3 is a sectional view taken along line um in FIG. 2, and FIG. 4 is a sectional view of a package according to another example. Fig. 5 is a schematic sectional view of the main parts of an example used for an endoscope, Fig. 6 is a perspective view showing a lead and a board for fixing the lead separated from the left and right sides according to another example, and Fig. 7 is the same as that of Fig. 6. 8 is a perspective view of a package according to another example; FIG. 9 is a front view of a portion of the lead attached to the tape; FIG. 1O is a plan view of FIG. 9; FIG. 11 is a sectional view of a package according to still another example. FIGS. 12 and 13 are cross-sectional views of conventional packages. In addition, in the reference numerals shown in the drawings, 20--------------------------Active area 21
------------Peripheral area 22.23--11-----Side surface 24--Insulating thin film 25-- Pad 26----- Metal pin 28.44--
----Insulating material 29--Transparent window 31--Semiconductor chip 33--
---------Wire 34-----External lead 35--
---------Resin 36.36a, 36b-----One substrate 42.
43-----1----Tape 44----------
-.- Adhesive or pressure-sensitive adhesive 45 -.-- Bump electrode. Agent Patent Attorney Hiroshi AisakaFigure 1Figure 2Figure 3Figure 4Figure 9Figure 10Figure 11

Claims (1)

【特許請求の範囲】[Claims] 1、電気的絶縁状態で外部リードが半導体チップの側面
に直接密着され、かつ前記外部リードと前記半導体チッ
プの電極とが電気的に接続されている半導体装置。
1. A semiconductor device in which an external lead is directly attached to a side surface of a semiconductor chip in an electrically insulated state, and the external lead and an electrode of the semiconductor chip are electrically connected.
JP62329079A 1987-12-25 1987-12-25 Semiconductor device Expired - Fee Related JP2565360B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62329079A JP2565360B2 (en) 1987-12-25 1987-12-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62329079A JP2565360B2 (en) 1987-12-25 1987-12-25 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH01171234A true JPH01171234A (en) 1989-07-06
JP2565360B2 JP2565360B2 (en) 1996-12-18

Family

ID=18217388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62329079A Expired - Fee Related JP2565360B2 (en) 1987-12-25 1987-12-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2565360B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6147398A (en) * 1997-03-21 2000-11-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device package
JP2004261512A (en) * 2003-03-04 2004-09-24 Pentax Corp Solid-state image pickup element and electronic endoscope

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62149843U (en) * 1986-03-14 1987-09-22
JPS6454749A (en) * 1987-08-26 1989-03-02 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62149843U (en) * 1986-03-14 1987-09-22
JPS6454749A (en) * 1987-08-26 1989-03-02 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6147398A (en) * 1997-03-21 2000-11-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device package
JP2004261512A (en) * 2003-03-04 2004-09-24 Pentax Corp Solid-state image pickup element and electronic endoscope

Also Published As

Publication number Publication date
JP2565360B2 (en) 1996-12-18

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