JPH01171234A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01171234A
JPH01171234A JP62329079A JP32907987A JPH01171234A JP H01171234 A JPH01171234 A JP H01171234A JP 62329079 A JP62329079 A JP 62329079A JP 32907987 A JP32907987 A JP 32907987A JP H01171234 A JPH01171234 A JP H01171234A
Authority
JP
Japan
Prior art keywords
chip
leads
semiconductor chip
close
side faces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62329079A
Other languages
Japanese (ja)
Other versions
JP2565360B2 (en
Inventor
Atsushi Komoro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Japan Ltd
Original Assignee
Texas Instruments Japan Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Japan Ltd filed Critical Texas Instruments Japan Ltd
Priority to JP62329079A priority Critical patent/JP2565360B2/en
Publication of JPH01171234A publication Critical patent/JPH01171234A/en
Application granted granted Critical
Publication of JP2565360B2 publication Critical patent/JP2565360B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4823Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a pin of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Abstract

PURPOSE: To improve positional accuracy of a semiconductor chip, by close contacting external leads directly with side faces of the semiconductor chip in electrically insulated relation, and electrically connecting the external leads with electrodes on the semiconductor chip.
CONSTITUTION: Each external lead 34 whose outer periphery is coated with an insulative material 24 is close contacted directly with a pair of opposing side faces 22, 23 of a semiconductor chip 31 consisting of an active area 20 and a peripheral area 21. While such close contact between the external leads and the semiconductor chip is kept by a special-purpose jig, bonding pads 25 on the chip 31 are wire bonded with the top faces of the leads 34 by means of wires 33. The device as a whole is sealed with resin 35 by the transfer molding process or the like. Since the leads 34 are close contacted with the side faces of the chip 31 in electrically insulated relation and they are connected with each other by wire bonding, there is no clearance between the chip 31 and the leads 34 and the size of the packaging structure is close to the outer diameter of the chip 31. Further, since the leads 34 are contacted directly with the chip side faces, it is possible to ensure satisfactory positional accuracy of the chip 31 in the package.
COPYRIGHT: (C)1989,JPO&Japio
JP62329079A 1987-12-25 1987-12-25 Semiconductor device Expired - Fee Related JP2565360B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62329079A JP2565360B2 (en) 1987-12-25 1987-12-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62329079A JP2565360B2 (en) 1987-12-25 1987-12-25 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH01171234A true JPH01171234A (en) 1989-07-06
JP2565360B2 JP2565360B2 (en) 1996-12-18

Family

ID=18217388

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62329079A Expired - Fee Related JP2565360B2 (en) 1987-12-25 1987-12-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2565360B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6147398A (en) * 1997-03-21 2000-11-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device package
JP2004261512A (en) * 2003-03-04 2004-09-24 Pentax Corp Solid-state image pickup element and electronic endoscope

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62149843U (en) * 1986-03-14 1987-09-22
JPS6454749A (en) * 1987-08-26 1989-03-02 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62149843U (en) * 1986-03-14 1987-09-22
JPS6454749A (en) * 1987-08-26 1989-03-02 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6147398A (en) * 1997-03-21 2000-11-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor device package
JP2004261512A (en) * 2003-03-04 2004-09-24 Pentax Corp Solid-state image pickup element and electronic endoscope

Also Published As

Publication number Publication date
JP2565360B2 (en) 1996-12-18

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