JPH01171065U - - Google Patents

Info

Publication number
JPH01171065U
JPH01171065U JP6788088U JP6788088U JPH01171065U JP H01171065 U JPH01171065 U JP H01171065U JP 6788088 U JP6788088 U JP 6788088U JP 6788088 U JP6788088 U JP 6788088U JP H01171065 U JPH01171065 U JP H01171065U
Authority
JP
Japan
Prior art keywords
solder plating
integrated circuit
hybrid integrated
plating layer
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6788088U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6788088U priority Critical patent/JPH01171065U/ja
Publication of JPH01171065U publication Critical patent/JPH01171065U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の分割半田メツキを実施した混
成集積回路の裏面図、第2図は第1図のA―A線
断面図、第3図は従来の半田めつきを実施した混
成集積回路の裏面図、第4図は第3図のB―B線
断面図である。 1……混成集積回路、2……裏面導体、3……
分割した半田めつき層、4……全面に形成した半
田めつき層。
Figure 1 is a back view of a hybrid integrated circuit that has undergone split solder plating according to the present invention, Figure 2 is a sectional view taken along line A--A in Figure 1, and Figure 3 is a rear view of a hybrid integrated circuit that has undergone conventional solder plating. 4 is a cross-sectional view taken along the line BB in FIG. 3. 1... Hybrid integrated circuit, 2... Back conductor, 3...
Divided solder plating layer, 4...Solder plating layer formed on the entire surface.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 裏面に形成した導体に半田めつき層を形成して
なる混成集積回路において、前記半田めつき層を
、前記導体の略全面にわたつて分割状態に配設し
た等面積の複数個の半田めつき層で構成したこと
を特徴とする混成集積回路。
In a hybrid integrated circuit in which a solder plating layer is formed on a conductor formed on the back surface, the solder plating layer is divided into a plurality of solder plating layers having equal areas and arranged over substantially the entire surface of the conductor. A hybrid integrated circuit characterized by being composed of layers.
JP6788088U 1988-05-23 1988-05-23 Pending JPH01171065U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6788088U JPH01171065U (en) 1988-05-23 1988-05-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6788088U JPH01171065U (en) 1988-05-23 1988-05-23

Publications (1)

Publication Number Publication Date
JPH01171065U true JPH01171065U (en) 1989-12-04

Family

ID=31293223

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6788088U Pending JPH01171065U (en) 1988-05-23 1988-05-23

Country Status (1)

Country Link
JP (1) JPH01171065U (en)

Similar Documents

Publication Publication Date Title
JPH01171065U (en)
JPH0193771U (en)
JPH0320464U (en)
JPS6382910U (en)
JPS6086545U (en) Soap with ring pattern
JPH0264032U (en)
JPS61183852U (en)
JPH024281U (en)
JPS63185276U (en)
JPS62150135U (en)
JPS6387860U (en)
JPS6223452U (en)
JPH03120066U (en)
JPS6240860U (en)
JPS6384972U (en)
JPS62165324U (en)
JPS62104444U (en)
JPS6249309U (en)
JPH0187544U (en)
JPH045024U (en)
JPH0178035U (en)
JPH0351872U (en)
JPH01139474U (en)
JPS63149599U (en)
JPS6423623U (en)