JPH01171036U - - Google Patents

Info

Publication number
JPH01171036U
JPH01171036U JP6787488U JP6787488U JPH01171036U JP H01171036 U JPH01171036 U JP H01171036U JP 6787488 U JP6787488 U JP 6787488U JP 6787488 U JP6787488 U JP 6787488U JP H01171036 U JPH01171036 U JP H01171036U
Authority
JP
Japan
Prior art keywords
package
sealing
sealing layer
groove
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6787488U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP6787488U priority Critical patent/JPH01171036U/ja
Publication of JPH01171036U publication Critical patent/JPH01171036U/ja
Pending legal-status Critical Current

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  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例のパツケージの組立
状態の断面図、第2図は第1図の構造の組立て前
の断面図、第3図は第2図のセラミツク基板の平
面図、第4図aは本考案のパツケージにおける封
着強度分布、第4図bは従来構造のパツケージに
おける封着強度分布、第5図は従来のパツケージ
組立て状態の断面図、第6図は第5図の構造のセ
ラミツク基板の平面図である。 1……セラミツク基板、2……メタライズ層、
3……アルミナセラミツク層、4……溝、5……
リード端子、6……セラミツクキヤツプ、7……
ガラスシール材。
FIG. 1 is a sectional view of a package according to an embodiment of the present invention in an assembled state, FIG. 2 is a sectional view of the structure of FIG. 1 before assembly, and FIG. 3 is a plan view of the ceramic substrate of FIG. Figure 4a shows the sealing strength distribution in the package of the present invention, Figure 4b shows the sealing strength distribution in the conventional package, Figure 5 is a sectional view of the conventional package assembled, and Figure 6 shows the sealing strength distribution in the package of the present invention. FIG. 3 is a plan view of the ceramic substrate of the structure. 1... Ceramic substrate, 2... Metallized layer,
3...Alumina ceramic layer, 4...Groove, 5...
Lead terminal, 6... Ceramic cap, 7...
Glass sealing material.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] セラミツク基板の上面にシール層を形成し、キ
ヤツプの開口面に装着したガラスシール材を熱圧
着により前記シール層に接着して封止を行う半導
体装置用パツケージにおいて、前記シール層の表
面に溝を形成し、ガラスシール材がこの溝内に充
填されるように構成したことを特徴とする半導体
装置用パツケーシ。
In a package for a semiconductor device in which a sealing layer is formed on the upper surface of a ceramic substrate and a glass sealing material attached to the opening surface of the cap is bonded to the sealing layer by thermocompression bonding for sealing, grooves are formed on the surface of the sealing layer. 1. A package for a semiconductor device, characterized in that a glass sealing material is formed in the groove and filled in the groove.
JP6787488U 1988-05-23 1988-05-23 Pending JPH01171036U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6787488U JPH01171036U (en) 1988-05-23 1988-05-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6787488U JPH01171036U (en) 1988-05-23 1988-05-23

Publications (1)

Publication Number Publication Date
JPH01171036U true JPH01171036U (en) 1989-12-04

Family

ID=31293217

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6787488U Pending JPH01171036U (en) 1988-05-23 1988-05-23

Country Status (1)

Country Link
JP (1) JPH01171036U (en)

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