JPS61190142U - - Google Patents
Info
- Publication number
- JPS61190142U JPS61190142U JP7471185U JP7471185U JPS61190142U JP S61190142 U JPS61190142 U JP S61190142U JP 7471185 U JP7471185 U JP 7471185U JP 7471185 U JP7471185 U JP 7471185U JP S61190142 U JPS61190142 U JP S61190142U
- Authority
- JP
- Japan
- Prior art keywords
- package
- semiconductor chip
- pad
- view
- led out
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 6
- 239000000919 ceramic Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
第１図〜第５図は本考案の実施例を示すもので
あつて、第１図は第１の実施例によるピギーバツ
ク型パツケージの分解斜視図、第２図は同パツケ
ージの完成状態における一部破断斜視図、第３図
は同パツケージの要部の拡大断面図、第４図はピ
ギーバツク型マイクロコンピユータを組立てる際
の両パツケージを分離して示す斜視図、第５図は
第２の実施例によるピギーバツク型パツケージの
分解斜視図である。第６図は従来のピギーバツク
型パツケージの概略断面図である。
なお、図面に示す符号において、２……半導体
チツプ、１１……上部セラミツク基板、１３，１
６，３３，４３，４６，５３……リード又は導体
、１７……メタライズ導体、２０……低融点ガラ
ス層、２１……上部セラミツク基板、２４……ボ
ンデイングパツドである。
1 to 5 show embodiments of the present invention, in which FIG. 1 is an exploded perspective view of a piggyback-type package according to the first embodiment, and FIG. 2 is a part of the same package in a completed state. 3 is an enlarged sectional view of the main parts of the same package, FIG. 4 is a perspective view showing both packages separated when assembling a piggyback microcomputer, and FIG. 5 is according to the second embodiment. FIG. 2 is an exploded perspective view of a piggyback type package. FIG. 6 is a schematic cross-sectional view of a conventional piggyback type package. In addition, in the symbols shown in the drawings, 2...semiconductor chip, 11... upper ceramic substrate, 13, 1
6, 33, 43, 46, 53...lead or conductor, 17...metallized conductor, 20...low melting point glass layer, 21...upper ceramic substrate, 24...bonding pad.
Claims (1)
、この半導体チツプに接続されたリードが前記パ
ツケージの外部に導出されると共に、前記半導体
チツプに接続されたパツドが前記パツケージの一
主面に設けられている半導体装置において、前記
半導体チツプと前記パツドとを接続するための配
線が前記パツケージの内部からその側面に導出さ
れて前記パツドにまで延びていることを特徴とす
る半導体装置。 A semiconductor chip is enclosed in a package, a lead connected to the semiconductor chip is led out of the package, and a pad connected to the semiconductor chip is provided on one main surface of the package. 1. A semiconductor device, wherein wiring for connecting the semiconductor chip and the pad is led out from inside the package to a side surface thereof and extends to the pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7471185U JPS61190142U (en) | 1985-05-20 | 1985-05-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7471185U JPS61190142U (en) | 1985-05-20 | 1985-05-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61190142U true JPS61190142U (en) | 1986-11-27 |
Family
ID=30615254
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7471185U Pending JPS61190142U (en) | 1985-05-20 | 1985-05-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61190142U (en) |
-
1985
- 1985-05-20 JP JP7471185U patent/JPS61190142U/ja active Pending