JPH01162961A - Diagnostic system for input/output device interface - Google Patents

Abstract

PURPOSE:To perform diagnosis of an input/output (I/O) device interface at a high speed by specifying the occurrence area of a fault that causes an error during a normal on-line action when some error is detected at the side of the I/O device. CONSTITUTION:The data are sent to an input/output device 10 from a CPU 16 via a transmission buffer 12 and an I/O controller 22 and at the same time stored in a register 20 via the buffer 12 and a reception buffer 14. When some error is detected at the side of the device 10, the data are read out of the register 20 via an internal bus of the CPU 16 and compared with the data to be actually transferred. Thus it is possible to decide a fault is produced at the side of the CPU 16 or at the side of an I/O device consisting of the controller 22 and the device 10. In such a way, the occurrence point of a fault causing an error is specified and therefore the diagnostic speed is increased.

Description

[Detailed Description of the Invention] Overview Regarding an input/output device interface diagnostic method for analyzing failures that cause errors between input/output devices and central processing units, when an error is detected on the input/output device side, normal online operation is performed. The purpose of this is to speed up diagnostic processing by identifying the location of the fault that causes the error during the process. , a register that stores the same data as the transmitted data, and a signal collision prevention buffer are provided between the transmit buffer input end and the receive buffer output side, and when data is sent from the central processing unit to the input/output device, the transmit buffer and The signal collision prevention buffer is closed at the same time as the reception buffer is opened, data to be sent is looped back and stored in a register, and the stored data is read out via an internal bus of the central processing unit.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input/output device interface diagnostic method for analyzing faults that cause errors between an input/output device (hereinafter referred to as an I10 device) and a central processing unit.

The central processing unit of the electronic computer and the 110 device are connected via a data bus, an I10 control device, and the like. I10 devices are important devices that exchange information between computers and the external environment, including humans, but they vary widely in both function and performance, and generally involve mechanical operation. There are many. The I10 controller is installed between the central processing unit and the I10 device to ensure smooth data transfer between them.

In addition, orders sent from the central processing unit to the I10 device are stored in registers within the central processing unit, and are sent to the I10 device via the data bus, I/O III till device, etc.
Therefore, if any abnormality is detected on the I10 device side, it is desired to quickly know the location of the fault that causes it.

Prior Art FIG. 4 shows a block diagram of a conventional input/output device interface diagnostic scheme.

12 is a transmission buffer, and 14 is a reception buffer, which are formed by a tri-state buffer. The transmission buffer 12 and the reception buffer 14 constitute a bidirectional buffer. 10 is an I10 device; 22 is an I10 that performs various adjustments associated with the connection between the I10 device 10 and the central processing unit 17;
Controller 4o is a data bus. I10 device 1
0 is connected to central processing unit 17 via I10 controller 22 and data bus 40. Further, within the central processing unit 17, a transmission buffer 12 and a reception buffer 14 are connected to a data bus 40.

The order sent from the central processing unit 17 to the I10 device 10 is sent to the I10 device 10 via the transmission buffer 12, data bus 401110 controller 22 in this order. At this time, the reception buffer 14 is set to a high impedance state and is apparently disconnected from the data bus 40.

Return data from the I10 device 10 is sent to the I10 controller 22, data bus 40. The data is read into a register (not shown) in the central processing unit 17 via the reception buffer 14. At this time, the transmission buffer 12 is set to a high impedance state.

If any error is detected on the I10 device 10 side during such data transmission/reception, the I10 device 10 sends a failure notification signal to the central processing unit 17 for failure analysis, and access to the I10 device 10 side is requested again. I was going.

Problems to be Solved by the Invention However, in the conventional input/output device interface diagnosis method as described above, when an error is detected on the I10 side, it is difficult to determine whether the cause is on the central processing unit side or on the I10 side. The problem was that it was difficult to distinguish. That is, orders from the central processing unit are sent to the data bus, I
The error is received on the r10 device side via the R10 controller, and it is difficult to determine in which part the error has occurred.

Generally, when this type of error occurs, the central processing unit
The diagnostic program must be started and the I10 device accessed again to analyze the cause of the error, which cannot be executed during online processing. In addition, a large amount of time is inevitably required to diagnose the system without knowing in which part of the system the fault has occurred. Moreover, in the case of an intermittent failure that occurs accidentally, there is no guarantee that the error will be reproduced even if the diagnostic program is executed, and it is difficult to determine the cause.

The present invention has been made in view of the above points, and its purpose is to identify the location of the failure that causes the error during normal online operation when an error of some kind is detected on the l101 side. The aim is to speed up diagnostic processing by doing so.

− for “to” FIG. 1 shows a block diagram of the principle of the present invention.

In the central processing unit 16 that sends and receives data to and from the I10 device @10 via the sending buffer 12 and receiving buffer 14, a register 2 stores the same data as the sent data.
0, and a signal collision prevention buffer 18 is provided between the input end of the transmission buffer 12 and the output side of the reception buffer 14.

When sending data from the central processing unit 16 to the input/output 8 and 10, the sending buffer 12 and the receiving buffer 14 are opened, and at the same time, the signal collision prevention buffer 118 is closed, and the data to be sent is folded back and stored in the register 20. The stored data is configured to be read out via the internal bus of the central processing unit 16.

Operation When data is sent from the central processing unit 16 to the input/output device 10, is the data sent to the transmission buffer? 12, at the same time as being sent to the I10 device 10 via the I10 controller 22,
It is also stored in the register 20 via the transmission buffer 12 and reception buffer 14. If any error is detected on the I10 device 10 side, the data stored in the register 20 is read out via the internal bus of the central processing unit 16 and compared with the data that was actually attempted to be sent before passing through the transmission buffer 12 etc. By this, on the central processing unit 16 side, l10
I10 consisting of 1 trolley 722 and 10 I10 devices
Determine which side is at fault.

Embodiments The present invention will be explained in detail below based on embodiments shown in the drawings.

FIG. 2 shows a block diagram of an embodiment of the input/output device interface diagnosis method according to the present invention, and FIG. 3 shows a timing chart according to the embodiment of FIG.

Reference numeral 12 designates a transmission buffer, 14 a reception buffer, and 18 a signal collision prevention buffer provided between the input side of the transmission buffer 12 and the output side of the reception buffer 14, all of which are formed of tri-state buffers. 24
21 is a data bus register that stores data passed through the reception buffer 14; 26 is a central processing unit 16;
An internal bus 27 is an arithmetic control section.

28 is a timing control unit that generates various timings for data transmission and reception with the I10 side, such as a signal collision prevention buffer? 18, a transmission buffer gate signal 32 that controls the transmission buffer 12, a reception buffer gate signal 34 that controls the reception buffer 14, a synchronization signal 36 when receiving an order on the I10 side, etc. is occurring. 38 is a synchronous signal buffer provided between the timing control section 28 and the I10 side, 10 is an I10 device, 22G, t110R device 1
I performs various adjustments associated with the connection between 0 and the central processing unit 16.
10 controllers.

Below, in the embodiment configured as described above, the operation when an order is sent from the central processing unit 16 to the I10 side will be explained in detail.

When an order is sent, the transmitting buffer gate signal 32 and the receiving buffer 7 gate signal 34 are at high level (see Figure 3), the transmitting buffer 12 and the receiving buffer 1'4 are open, and the data is stored in the data register 24. The ordered order is output to the data bus and sent to the I10 device 10 via the transmission buffer 12 and the I10 controller 22. Is there a sending buffer at the same time? The order output from 12 is also sent to data bus register 21 via reception buffer 14, and data bus register 21 internally latches the order using synchronization signal 36 (see FIG. 3). At this time, since the data line in the central processing unit 16 is bidirectional, if the receiving buffer 14 is opened when sending an order, a collision of orders will occur. Therefore, the signal collision is prevented by setting the signal collision prevention buffer gate signal 30 to a low level. Buffer 18 is closed to prevent collisions.

When the order sending is finished, the sending buffer gate signal 32 and the receiving buffer gate signal 34 become low level (see FIG. 3), and when receiving the return data from the I10 device 10 to the central processing unit 16, the receiving buffer gate signal 32 and the receiving buffer gate signal 34 become low level. 34
, the signal collision prevention buffer gate signal 30 becomes high level (see FIG. 3), the reception buffer 14 and the signal collision prevention buffer 18 are opened, and the central processing unit 16 enters the reception state.

If any error is detected on the I10 device 10 side, the order stored in the data bus register 21 is read into the arithmetic unit (not shown) via the internal bus 26 and compared with the order actually intended to be sent. do. If the comparison results do not match, the central processing unit 1
It is considered that there is some kind of failure in the order sending section (including the sending buffer 12) in the sync signal 6 (including the sending buffer 12) or the synchronization signal 36 generating section that causes the error. Further, when an error is detected, if the results of comparing the orders match, it is considered that there is a failure on the I10 side (including the data bus) which is external to the central processing unit 16.

The operations of each part described above are performed every time an order is sent during normal online processing, and the central processing unit 16 always holds its own data for failure analysis.
There is no need to collect data for failure analysis, and at least it is possible to immediately know whether the failure is within the central processing unit 16 or not.

Effects of the Invention Since the input/output device interface diagnosis method of the present invention is configured as detailed above, data for failure analysis can be obtained during normal online operation, and data can be reused to collect data for diagnosis when an error occurs. There is no need to start up the system, and failure analysis can be performed in real time. Furthermore, the central processing unit, I
Since it is possible to determine which side of the 10 side is faulty and to specify the location where diagnosis should be performed, the resolution of diagnosis can be improved and a highly reliable system can be realized. play.

[Brief explanation of the drawing]

Fig. 1 is a 10-step diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the input/output device interface diagnosis method according to the invention, Fig. 3 is a timing chart according to the embodiment of Fig. 2, and Fig. 4 is a conventional diagram. 1 shows a block diagram of an input/output device interface diagnostic scheme of the invention. 10... I10 device, 12... Transmission buffer, 14... Reception buffer, 16.17... Central processing unit, 18... Signal collision prevention buffer, 20... Register, 21... Data bus register, 22... I10 controller, 24... Data register, 26... Internal bus, 27... Arithmetic control section, 28... Timing control section, 30... Signal collision prevention buffer gate Signal, 32...
- Transmission buffer 7 gate signal, 34... Reception buffer gate signal, 36... Synchronization signal, 38... Buffer, 40... Data bus. 16:f Missing Reason for Reception〃2Harachori゛Fuku Map Figure 1 □Water on the Order -H-1 Transfer Type = Receipt 1st 20I
) Firepower and A column I; Yo δ timing chart Y-t Figure 3

Claims (1)

[Claims] Data transmission and reception with the input/output device (10) is performed using a transmission buffer (1
2) and a reception buffer (14) in the central processing unit (16), the register (2) stores the same data as the sent data.
0), and a signal collision prevention buffer (18) between the input side of the transmission buffer (12) and the output side of the reception buffer (14), and transmits data from the central processing unit (16) to the input/output device (10). time, sending buffer (12) and receiving buffer (14)
At the same time as opening, the signal collision prevention buffer (18) is closed, the data to be sent is looped back and stored in the register (20), and the stored data is read out via the internal bus of the central processing unit (16). An input/output device interface diagnostic method characterized by: