JPH0116051B2 - - Google Patents
Info
- Publication number
- JPH0116051B2 JPH0116051B2 JP1763580A JP1763580A JPH0116051B2 JP H0116051 B2 JPH0116051 B2 JP H0116051B2 JP 1763580 A JP1763580 A JP 1763580A JP 1763580 A JP1763580 A JP 1763580A JP H0116051 B2 JPH0116051 B2 JP H0116051B2
- Authority
- JP
- Japan
- Prior art keywords
- potential
- power supply
- terminal
- voltage
- output terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005669 field effect Effects 0.000 claims description 7
- 238000000034 method Methods 0.000 description 6
- 239000004973 liquid crystal related substance Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005513 bias potential Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
- Liquid Crystal (AREA)
- Liquid Crystal Display Device Control (AREA)
Description
【発明の詳細な説明】
本発明は分圧回路に関し、特に相補型絶縁ゲー
ト型電界効果トランジスタを使用した半導体装置
に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a voltage divider circuit, and more particularly to a semiconductor device using complementary insulated gate field effect transistors.
従来、電卓等の液晶表示回路では、駆動回路と
液晶の接続端子数の制約から、複数個の電源電圧
を用いるスタテイツク駆動方式が一般に用いられ
るようになつた。通常は第1図に示すように抵抗
R1〜R3を直列に接続した分圧回路を用いこれに
より複数個の電圧源を得るのがこの方式によると
抵抗を高くする事によりこの部分の消費電力が減
る反面、スタテイツク駆動方式を使用している為
クロツクの切り換わる時分圧電圧V1及びV2に液
晶素子の電極間容量結合による影響が出て抵抗で
分割した電圧レベルを一定に保てない。このレベ
ルを一定に保つ為には分圧回路にある程度の電力
を消費させねばならずこれによつて低消費電力化
に限界を来たしている。他の従来例は高抵抗素子
により電源を分圧し電位のみ取り出しこれにボル
テージフオロワを接続する方法でスタテイツク駆
動方式の周波数が遅い時はボルテージフオロワの
消費電力を少なくする事ができ全体としては低消
費電力となる、しかし液晶表示素子は等価的に容
量素子と等しい為ダイナミツク動作を行なわせる
とその両端の電位は互に反対側の電極の変化に伴
ない変化する。この時定電流源から電流を供給す
る方向へ変化した場合この定電流源の大きさによ
りこの回路の応答速度が決まる。実際には回路の
消費電力を少なくする為定電流源は小さくなつて
いるので応答速度はかなり遅いものとなつてい
る。従つてこの欠点を補なう為分圧出力端子に大
容量を接続しなければならない。しかしこの方法
を取ると外部端子と容量が必要となり集積回路の
利点の一つである外付部品が少なくて済むことに
反する為実用的ではない。 Conventionally, in liquid crystal display circuits such as calculators, a static drive method using a plurality of power supply voltages has generally been used due to restrictions on the number of connection terminals between the drive circuit and the liquid crystal. Usually the resistance is as shown in Figure 1.
This method uses a voltage divider circuit in which R 1 to R 3 are connected in series to obtain multiple voltage sources.While increasing the resistance reduces power consumption in this part, it uses a static drive method. Therefore, when the clock switches, the divided voltages V1 and V2 are affected by the capacitive coupling between the electrodes of the liquid crystal element, and the voltage level divided by the resistor cannot be kept constant. In order to keep this level constant, the voltage divider circuit must consume a certain amount of power, which limits the ability to reduce power consumption. Another conventional method is to divide the power supply using a high resistance element, take out only the potential, and connect a voltage follower to it. When the frequency of the static drive system is slow, the power consumption of the voltage follower can be reduced, and the overall effect is However, since the liquid crystal display element is equivalent to a capacitive element, when a dynamic operation is performed, the potential at both ends of the liquid crystal display element changes as the electrodes on the opposite side change. When the direction changes from this time constant current source to supplying current, the response speed of this circuit is determined by the size of this constant current source. In reality, the constant current source has become smaller in order to reduce the power consumption of the circuit, so the response speed is quite slow. Therefore, in order to compensate for this drawback, a large capacitance must be connected to the divided voltage output terminal. However, this method is impractical because it requires external terminals and capacitors, which goes against one of the advantages of integrated circuits, which is the need for fewer external components.
本発明の目的は低消費電力で高精度な分圧回路
を提供することにある。 An object of the present invention is to provide a voltage dividing circuit with low power consumption and high accuracy.
本発明による分圧回路は、第1と第2の電源端
子の間に直列に接続された高抵抗素子を有し、該
第1および第2の電源端子の電圧間の値の分圧電
圧を出力する抵抗分圧回路と、第1および第2の
入力端子と出力端子を有し、該第1の入力端子の
電位が該第2の電源端子の電位の方向に変化する
時、該出力端子の電位は該第1の電源端子の電位
の方向へと変化し、該第2の入力端子の電位が該
第2の電源端子の電位の方向に変化する時、該出
力端子の電位が該第2の電源端子の電位の方向へ
と変化する差動増幅回路と、該第1の電源端子と
電圧出力端子との間に接続されその電流量が制御
信号に応答して増加する電流源と、該電圧出力端
子と該第2の電源端子との間に接続され、ゲート
の電位が該第1の電源端子の電位方向に変化する
ことによつて電流量が増大するような導電型を有
する電界効果トランジスタと、該差動増幅器の出
力端子を該電界効果トランジスタのゲートに接続
する手段と、該差動増幅器の第1の入力端子に該
分圧電圧を印加する手段と、該差動増幅回路の第
2の入力端子を該分圧出力端子に接続する手段と
を有し、上記制御信号に同期して該電圧出力端子
の駆動能力を増大せしめることを特徴とする。 The voltage divider circuit according to the present invention has a high resistance element connected in series between a first and a second power supply terminal, and divides a voltage between the voltages of the first and second power supply terminals. It has a resistor voltage divider circuit that outputs, first and second input terminals, and an output terminal, and when the potential of the first input terminal changes in the direction of the potential of the second power supply terminal, the output terminal When the potential of the output terminal changes in the direction of the potential of the first power supply terminal and the potential of the second input terminal changes in the direction of the potential of the second power supply terminal, the potential of the output terminal changes in the direction of the potential of the first power supply terminal. a differential amplifier circuit that changes in the direction of the potential of a second power supply terminal; a current source that is connected between the first power supply terminal and the voltage output terminal and whose current amount increases in response to a control signal; an electric field connected between the voltage output terminal and the second power supply terminal and having a conductivity type such that the amount of current increases when the potential of the gate changes in the direction of the potential of the first power supply terminal; an effect transistor, means for connecting the output terminal of the differential amplifier to the gate of the field effect transistor, means for applying the divided voltage to a first input terminal of the differential amplifier, and the differential amplifier circuit. and means for connecting a second input terminal of the voltage output terminal to the voltage division output terminal, and increasing the driving capability of the voltage output terminal in synchronization with the control signal.
本発明によれば相補型電界効果トランジスタを
使用する差動増幅回路を含む分圧回路において電
源の電位を高抵抗素子を用いて分圧しこれを基準
電源として用い上記差動増幅器の一方の入力端子
に供給し、該差動増幅路の出力を一導電型の電界
効果トランジスタを入力トランジスタとし他の導
電型の電界効果トランジスタを定電流源とした反
転増幅器に入力し、定電流源に並列に内部の制御
信号により制御される電流源を設けこの反転増幅
器の出力を上記差動増幅器の他の一方の入力端子
に供給するようにした分圧回路が得られる。 According to the present invention, in a voltage divider circuit including a differential amplifier circuit using complementary field effect transistors, the potential of a power supply is divided using a high resistance element, and this is used as a reference power supply to one input terminal of the differential amplifier. The output of the differential amplifier path is input to an inverting amplifier with a field effect transistor of one conductivity type as an input transistor and a field effect transistor of the other conductivity type as a constant current source, and an internal circuit connected in parallel to the constant current source. A voltage dividing circuit is obtained in which a current source controlled by a control signal is provided and the output of this inverting amplifier is supplied to the other input terminal of the differential amplifier.
第2図を参照して本発明の一実施例を示す。高
抵抗R21,R22,R23により電源の電位−VDを分割
するこの分割された電圧V1,V2を基準としHiqh
側のレベルを出す端子V1はnchトランジスタM2
を入力とした差動増幅器を持つポルテージフオロ
ワで、電圧V2はPchトランジスタM11を入力とし
た差動増幅器を持つボルテージフオロワを介して
出力V1′,V2′される。これはボルテージフオロワ
の動作範囲が入力に使用したトランジスタにしき
い値と電源電圧の間にある為で低消費電力のシス
テムでは1/3|VD|がこの入力に用いたトランジ
スタのしきい値より低い場合が考えられるのでこ
の組合せを取つた。電源電圧が高い場合などでこ
のボルテージフオロワの動作範囲に十分余裕が有
る場合はこの組合せ以外でも使用できる。出力バ
ツフア部はドライブ用トランジスタM8,M16と
定電流源トランジスタM9,M15を組合わせて使
用しているが、この場合定電流源と並列にさらに
もう1つの電流源トランジスタM19,M20を接続
し互に逆相のコントロールパルスφ1,φ2により
この電流源トランジスタM19,M20を制御させ
る。この可変電流源により定電流源のみでは駆動
力が不足するタイミングの時コントロールパルス
φ1,φ2が入り不足分を補なう。従つて本方式に
依れば外部に部品を接続しなくとも安定な中間電
位が得られる事になる。上記例ではそれぞれ2つ
のトランジスタM7とM19,M15とM20によつて可
変電流源を構成したが、それぞれ1つのトランジ
スタM7,M15のみを用い、この1つのトランジ
スタのゲートをA点又はB点のバイアス電位から
接地(M7の場合)、および−VD(M15の場合)に
スイツチによつて切換ることによつてトランジス
タを流れる電流量を制御しても良い。またバイア
ス抵抗R14,R15を可変とする。例えば、抵抗
R14,R15にそれぞれスイツチを介して他の抵抗
を並列接続し、このスイツチをオンさせて実効抵
抗を小さくしてそれぞれ1つのトランジスタM7,
M15の電流量を増加制御する方法を用いても良
い。 An embodiment of the present invention will be shown with reference to FIG. The potential of the power supply -V D is divided by high resistances R 21 , R 22 , and R 23 . Using these divided voltages V 1 and V 2 as a reference, Hiqh
The terminal V1 that outputs the side level is the nch transistor M2
The voltage V 2 is output as V 1 ′, V 2 ′ through the voltage follower with a differential amplifier that uses the Pch transistor M 11 as an input. This is because the operating range of the voltage follower is between the threshold value of the transistor used for input and the power supply voltage, so in a low power consumption system, 1/3 |V D | is the threshold value of the transistor used for this input. This combination was selected because it is possible that the value is lower. If there is sufficient margin in the operating range of this voltage follower, such as when the power supply voltage is high, combinations other than this can be used. The output buffer section uses a combination of drive transistors M 8 , M 16 and constant current source transistors M 9 , M 15 , but in this case, another current source transistor M 19 , in parallel with the constant current source is used. M 20 is connected and the current source transistors M 19 and M 20 are controlled by control pulses φ 1 and φ 2 having mutually opposite phases. With this variable current source, control pulses φ 1 and φ 2 are input at timings when the driving force is insufficient with only the constant current source to compensate for the shortage. Therefore, according to this method, a stable intermediate potential can be obtained without connecting any external components. In the above example, the variable current sources were configured by two transistors M 7 and M 19 and M 15 and M 20 , respectively, but only one transistor M 7 and M 15 were used, and the gate of this one transistor was set to A. The amount of current flowing through the transistor may be controlled by switching from the bias potential at point or point B to ground (in the case of M7 ) and -V D (in the case of M15 ) using a switch. Also, bias resistors R 14 and R 15 are made variable. For example, resistance
Other resistors are connected in parallel to R 14 and R 15 through switches, and the switches are turned on to reduce the effective resistance and one transistor M 7 ,
A method of increasing the current amount of M15 may also be used.
以上詳細に説明したように本発明によれば能動
素子を用いて電圧源を構成する事により従来の回
路に較べ低消費電力で高性能の分圧回路が実現で
きる。 As described in detail above, according to the present invention, by configuring a voltage source using active elements, a voltage dividing circuit with lower power consumption and higher performance than conventional circuits can be realized.
本発明では分圧電圧V1側の出力バツフアはPch
トランジスタM8に入力しnchトランジスタM7を
定電流源として使用しているがトランジスタM7
に入力しトランジスタM8を定電流源に使用して
もよい。分圧電圧V2側についても同様な事が言
える。また出力バツフアを2段構成とする事によ
り駆動能力が向上する。さらにトランジスタM6,
R14ならびにM14抵抗R15により構成されている2
つの定電圧回路は第3図に示すようにnchトラン
ジスタM6,M14、抵抗R16の回路構成を取ること
により抵抗を1本省くことができる。出力端V1,
V2に容量を接続する事により、コントロールパ
ルス入力時におけるレベルの変化を吸収する方法
を取る事もできる。また電源に高い周波数の雑音
が有る場合には分圧用高抵抗に並列に容量を接続
すれば良い。 In the present invention, the output buffer on the side of divided voltage V1 is Pch
Input to transistor M8 , nch transistor M7 is used as a constant current source, but transistor M7
The transistor M8 may be used as a constant current source. The same thing can be said about the divided voltage V2 side. Furthermore, by configuring the output buffer in two stages, the driving ability is improved. Furthermore, the transistor M 6 ,
2 consisting of R 14 and M 14 resistor R 15
As shown in FIG. 3, the two constant voltage circuits can be configured to include nch transistors M 6 and M 14 and a resistor R 16 , thereby eliminating one resistor. Output end V 1 ,
By connecting a capacitor to V2 , it is also possible to absorb the level change when the control pulse is input. Furthermore, if there is high frequency noise in the power supply, a capacitor may be connected in parallel to the high voltage dividing resistor.
第1図は従来からの分圧回路を示す図、第2図
は本発明の一実施例を示す回路図、第3図は第2
図の実施例における定電圧回路の他の一例を示す
図である。
R1,R2,R3,R11,R12,R13……抵抗素子、
R14,R15,R16……定電圧回路のバイアス抵抗、
M1,M2,M3,M6,M7,M9,M10,M16,
M18,M19……nchトランジスタ、M4,M5,M8,
M11,M12,M13,M14,M15,M17,M20……
Pchトランジスタ、C1,C2,C3,C4,C5……容
量。
Fig. 1 is a diagram showing a conventional voltage dividing circuit, Fig. 2 is a circuit diagram showing an embodiment of the present invention, and Fig. 3 is a diagram showing a conventional voltage dividing circuit.
It is a figure which shows another example of the constant voltage circuit in the Example of a figure. R 1 , R 2 , R 3 , R 11 , R 12 , R 13 ... Resistance element,
R 14 , R 15 , R 16 ...bias resistance of constant voltage circuit,
M1 , M2 , M3 , M6 , M7 , M9 , M10 , M16 ,
M18 , M19 ...nch transistor, M4 , M5 , M8 ,
M11 , M12 , M13 , M14 , M15 , M17 , M20 ...
Pch transistor, C 1 , C 2 , C 3 , C 4 , C 5 ...capacitance.
Claims (1)
た高抵抗素子を有し、該第1および第2の電源端
子の電圧間の値の分圧電圧を出力する抵抗分圧回
路と、第1および第2の入力端子と出力端子を有
し、該第1の入力端子の電位が該第2の電源端子
の電位の方向に変化する時該出力端子の電位は該
第1の電源端子の電位の方向へと変化し、該第2
の入力端子の電位が該第2の電源端子の電位の方
向に変化する時、該出力端子の電位が該第2の電
源端子の電位の方向へと変化する差動増幅回路
と、該第1の電源端子と電圧出力端子との間に接
続されその電流量が制御信号に応答して増加する
電流源と、該電圧出力端子と該第2の電源端子と
の間に接続され、ゲートの電位が該第1の電源端
子の電位方向に変化することによつて電流量が増
大するような導電型を有する電界効果トランジス
タと、該差動増幅器の出力端子を該電界効果トラ
ンジスタのゲートに接続する手段と、該差動増幅
器の第1の入力端子に該分圧電圧を印加する手段
と、該差動増幅回路の第2の入力端子を該分圧出
力端子に接続する手段とを有し、上記制御信号に
同期して該電圧出力端子の駆動能力を増大せしめ
ることを特徴とする分圧回路。1 A resistive voltage divider circuit having a high resistance element connected in series between a first and a second power supply terminal, and outputting a divided voltage having a value between the voltages of the first and second power supply terminals. , has first and second input terminals and an output terminal, and when the potential of the first input terminal changes in the direction of the potential of the second power supply terminal, the potential of the output terminal changes to the potential of the first power supply terminal. The potential of the terminal changes in the direction of the second
a differential amplifier circuit in which the potential of the output terminal changes in the direction of the potential of the second power supply terminal when the potential of the input terminal of the first power supply terminal changes in the direction of the potential of the second power supply terminal; a current source connected between the power supply terminal and the voltage output terminal and whose current amount increases in response to a control signal; a field effect transistor having a conductivity type such that the amount of current increases as the voltage changes in the direction of the potential of the first power supply terminal; and an output terminal of the differential amplifier is connected to the gate of the field effect transistor. means for applying the divided voltage to a first input terminal of the differential amplifier; and means for connecting a second input terminal of the differential amplifier circuit to the divided voltage output terminal; A voltage dividing circuit characterized in that the driving capability of the voltage output terminal is increased in synchronization with the control signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1763580A JPS56115176A (en) | 1980-02-15 | 1980-02-15 | Voltage dividing circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1763580A JPS56115176A (en) | 1980-02-15 | 1980-02-15 | Voltage dividing circuit |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7679884A Division JPS6035813A (en) | 1984-04-17 | 1984-04-17 | Differential amplifier circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56115176A JPS56115176A (en) | 1981-09-10 |
JPH0116051B2 true JPH0116051B2 (en) | 1989-03-22 |
Family
ID=11949317
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1763580A Granted JPS56115176A (en) | 1980-02-15 | 1980-02-15 | Voltage dividing circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56115176A (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58195888A (en) * | 1982-05-12 | 1983-11-15 | 株式会社日立製作所 | Liquid crystal driving circuit |
JPS6035813A (en) * | 1984-04-17 | 1985-02-23 | Nec Corp | Differential amplifier circuit |
JPH0219190U (en) * | 1988-07-26 | 1990-02-08 | ||
US6342782B1 (en) | 1999-01-08 | 2002-01-29 | Seiko Epson Corporation | Power supply device for driving liquid crystal, liquid crystal device and electronic equipment using the same |
JP3573055B2 (en) * | 1999-03-26 | 2004-10-06 | セイコーエプソン株式会社 | Display drive device, display device, and portable electronic device |
-
1980
- 1980-02-15 JP JP1763580A patent/JPS56115176A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS56115176A (en) | 1981-09-10 |
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