JPH01160239A - Carrier lock detection circuit - Google Patents

Abstract

PURPOSE:To attain the synchronizing detection in a short time with simple circuit constitution by integrating a phase error detection signal detected by a demodulation circuit and comparing its integration value with a prescribed threshold value so as to detect the synchronization. CONSTITUTION:The frequency sweep in the demodulation circuit 101 is implemented when the frequency fluctuation range exceeds the synchronization enable range, and a phase error signal being an output of a phase error detection circuit 103 becomes a beat signal in response to the frequency deviation in the synchronization enable range and the frequency fluctuation range in case of the implementation of the frequency sweep. Thus, a signal being the result of integrating the beat signal at a prescribed time interval becomes a beat signal and the amplitude is larger as the frequency deviation is smaller. Then the signal integrated by an integration device 107 is outputted to a comparator circuit 108. The comparator circuit 108 is configurated such that it compares the relation of quantity between the output level of the integration device 107 and a preset threshold level and outputs the result of comparison as a signal discriminating the propriety of consecution of the frequency sweeping of the output of a loop filter 105 to a control circuit 109.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a carrier lock detection circuit, particularly a carrier lock detection circuit for detecting synchronization of a demodulation circuit in a digital communication system that uses a transmission line with large frequency fluctuations such as a satellite line. Concerning improvements in detection circuits.

[Prior Art] As is well known, in satellite communications, deviations in carrier frequency occur due to reasons such as poor stability of local oscillators on the satellite.

For this reason, various measures are taken in the demodulation circuit to ensure early establishment of synchronization. For example, some demodulation circuits using a synchronous detection method are configured to sweep the reproduced carrier frequency and establish synchronization quickly even if the frequency deviation becomes larger than the loop bandwidth.

Further, such demodulation circuits include various types of demodulation circuits in addition to the synchronous detection type. In such a device, it is conceivable to provide a means for frequency sweeping the manually modulated signal at the input stage of the demodulation circuit as a frequency sweeping method.

All of these demodulation circuits are configured to detect whether or not synchronization has been established in an external circuit that receives the restored demodulated signal, and to determine whether or not to continue the frequency sweep operation based on the detection result.

[Problems to be Solved] By the way, as mentioned above, in a demodulation circuit configured to sweep the frequency of an input modulation signal or a regenerated carrier wave and to establish synchronization as soon as possible, the frequency changes as soon as synchronization is established. It is necessary to take measures such as stopping the sweep.

However, in the demodulation circuit using the conventional synchronization detection method,
There are problems in that it takes a long time to detect synchronization and the external circuit for detecting synchronization becomes complicated.

For example, when error correction coding technology is used in satellite communications, the redundancy of transmitted information increases.
There is a problem in that it takes time to confirm the establishment of synchronization.

In addition, when synchronization detection is performed using synchronization words, it is determined that synchronization has been established when synchronization words are detected consecutively, but in this case, it is necessary to take into account situations such as incorrect detection or non-detection of synchronization words. Therefore, there was a problem in that the external circuit became complicated.

The present invention has been made in view of these conventional problems, and its purpose is to obtain a carrier lock detection circuit that can perform synchronization detection in a short time with a relatively simple circuit configuration.

[Means for Solving Problems] To achieve the above object, the present invention provides a carrier lock detection circuit for a demodulation circuit configured to establish synchronization by sweeping the frequency of an input modulation signal or a regenerated carrier wave, comprising: An integrator that integrates and outputs the phase error signal detected and output from the demodulation circuit performs synchronization detection by comparing the output signal of this integrator with a preset threshold level, and directs the synchronization detection to the demodulation circuit. and a comparison circuit that outputs a signal, and is configured to determine whether the frequency sweep operation can be continued based on the output signal of the comparison circuit.

[Example] Next, preferred embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a preferred example of a carrier lock detection circuit according to the present invention.

In the same figure, 101 is a demodulation circuit having a frequency sweep function. ) 104 and a control circuit 109.

In the demodulator 101 having the frequency sweep function as described above, it is necessary to take measures such as stopping the frequency sweep at the same time as synchronization is established as described above.

The feature of the present invention is that the carrier lock detection circuit is
07 and comparator 108,
The purpose is to perform synchronization detection in a short time with a relatively simple circuit configuration.

Here, the integrator 107 is formed to integrate and output the output of the phase error detection circuit 103. In other words, the frequency sweep in the demodulation circuit 101 is performed when the frequency fluctuation range of the input modulation signal exceeds the synchronizable range, but when this frequency sweep is performed, the phase error signal exceeds the synchronizable range. The beat signal becomes a beat signal according to the deviation frequency of the frequency fluctuation range. Therefore, a signal obtained by integrating a beat signal over a certain time interval also becomes a beat signal.
Its amplitude increases as the shift frequency decreases.

Then, the signal integrated by the integrator 107 is output to the comparison circuit 108.

The comparison circuit 108 compares the output level of the integrator 107 with a preset threshold level, and uses the comparison results to determine whether the frequency sweep operation can be continued and whether the loop filter 105 can output the output. Control circuit 10 as a signal
It is configured to output to 9.

The present embodiment has the above configuration, and its operation will be explained next.

Note that since the demodulation circuit 101 is a well-known circuit, its operation will be briefly explained.

First, when a modulated wave signal is input to the demodulation circuit 101 via the input terminal 1, this modulated wave signal is input to the orthogonal demodulator 102.

The regenerated carrier wave output from the VCO 104 is also input to the orthogonal demodulator 102, and the modulated wave signal inputted from the input terminal 1 is orthogonally demodulated by this regenerated carrier wave, and the demodulated signals I signal and Q signal are generated. as output terminal 2
．． 3 and output to the phase error detection circuit 103.

At this time, if the frequency deviation between the input modulated wave signal and the reproduced carrier wave is within the lock range of the carrier wave recovery circuit, the reproduced carrier wave frequency can follow the input modulated wave frequency, and correct demodulation operation is performed.

However, if the frequency difference is not within the lock range, the correct demodulation operation will not be performed, so in this case a sweep command is applied to the input terminal 4. In response, the control circuit 109 generates a frequency sweep signal and at the same time outputs a command signal to the loop filter 105 to output 0.

This frequency sweep signal and the output of the loop filter 105 are
Since the signals are added in the adder 106 and outputted as the control voltage of C0104, the frequency of the reproduced carrier wave is swept.

On the other hand, the output of the phase error detection circuit 103 is the frequency difference Δf
With respect to the input of , the beat signal has a frequency of 4Δf in 4-phase PSK and 2Δf in 2-phase PSK.

The process of forming this beat signal will be explained by taking the case of 4-phase PSK as an example with reference to FIG.

First, the phase error detection circuit 103 is of a Costas type, for example, and its phase error detection characteristics are as shown in FIG. There is. In the figure, the polarity code "+" represents the leading phase control direction, and "-" represents the lagging phase control method. Then, when the input signal rotates in a layered manner at a speed of 2πΔft as shown in FIG. 2(b), the output signal has a period TS (TS = 1/4Δf) as shown in FIG. 2(c). ), resulting in a monotonically increasing signal that repeats.

When the frequency of the reproduced carrier wave is swept, Δf changes, so the period TS of the output signal also changes. From this, the output signal of the phase error detection circuit 103 becomes as shown in FIG. However, the figure shows the case where Δf is decreasing, and time to represents the point in time when Δf becomes O.

Now, such an output signal is processed by the integrator 107 at time intervals Δt (from time t to time t+Δt in the figure).
When integrated at , the output of the integrator 107 becomes a beat signal that becomes maximum or minimum near time to, as shown in FIG.

Therefore, as shown in FIG. 4, if a threshold value is set in the comparator circuit 108, the output level Δf of the integrator 107 becomes 0.
Since the threshold value is exceeded when Δf is close to 0, the output of the comparison circuit 108 changes from a low level to a high level when Δf approaches 0, as shown in FIG. In other words, it is possible to notify the control circuit 109 that Δf is near the lock point.

In this manner, the carrier lock detection circuit of this embodiment can perform synchronization detection in a short time with a relatively simple configuration using the integrator 107 and the comparison circuit 108.

Then, when synchronization is detected in this way, the control circuit 109 stops the frequency sweep operation, and the loop filter 1
05, the demodulation circuit 101 enters a normal synchronization state.

In this embodiment, the demodulation circuit 101 is of a type that sweeps the reproduced carrier wave, but the present invention is not limited to this. Needless to say, the present invention can be similarly applied to demodulation circuits.

Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications can be made within the scope of the gist of the present invention.

[Effects of the Invention] As explained above, according to the present invention, a relatively simple circuit configuration is provided in which the phase error detection signal detected by the demodulation circuit is integrated and the integrated value is compared with a predetermined threshold value. This has the effect of performing synchronization detection in a short time.

Furthermore, according to the present invention, since the circuit configuration is relatively simple,
Another effect is that the cost of the entire circuit can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a preferred example of the carrier lock detection circuit and demodulation circuit according to the present invention; FIG. 2 is an explanatory diagram of the operation of the phase error detection circuit when the frequency difference Δf takes a finite value; 3 is an output waveform diagram of the phase error detection circuit, FIG. 4 is an output waveform diagram of the integrator, and FIG. 5 is an explanatory diagram of the operation of the comparison circuit. 101: Demodulation circuit 103: Phase error detection circuit 107: Integrator 108: Comparison circuit 109: Control circuit

Claims (1)

[Scope of Claims] A carrier lock detection circuit for a demodulation circuit formed to establish synchronization by sweeping the frequency of an input modulation signal or a regenerated carrier wave, the carrier lock detection circuit detecting a phase error signal detected and output from the demodulation circuit. The comparison circuit includes an integrator that outputs the integral, and a comparison circuit that performs synchronization detection by comparing the output signal of the integrator with a preset threshold level and outputs a synchronization detection signal to the demodulation circuit. A carrier lock detection circuit characterized in that it is formed to determine whether a frequency sweep operation can be continued based on an output signal of the circuit.