JPH0530098B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a carrier lock detection circuit, particularly a carrier lock detection circuit that detects the synchronization of a demodulation circuit in a digital communication system that uses a transmission line with large frequency fluctuations such as a satellite line. Regarding improvements.

[Prior Art] As is well known, in satellite communications, deviations in carrier frequency occur due to reasons such as poor stability of local oscillators on the satellite.

For this reason, various measures are taken in the demodulation circuit to ensure early establishment of synchronization. For example, some demodulation circuits using a synchronous detection method are configured to sweep the reproduced carrier frequency so that synchronization can be established quickly even if the frequency deviation becomes larger than the loop bandwidth.

Further, such demodulation circuits include various types of demodulation circuits in addition to the synchronous detection type. In such a device, as a frequency sweep method, it is possible to provide means for frequency sweeping the input modulated signal at the input stage of the demodulation circuit.

All of these demodulation circuits are configured to detect whether or not synchronization has been established in an external circuit that receives the restored demodulated signal, and to determine whether or not to continue the frequency sweep operation based on the detection result.

[Problems to be Solved] By the way, as mentioned above, in a demodulation circuit that is configured to sweep the frequency of an input modulation signal or a regenerated carrier wave and establish synchronization as soon as possible, the frequency changes as soon as synchronization is established. It is necessary to take measures such as stopping the sweep.

However, demodulation circuits using conventional synchronization detection methods have had problems such as requiring a long time to detect synchronization and complicating the external circuitry for synchronization detection.

For example, when error correction coding technology is used in satellite communications, the redundancy of transmitted information increases, so there is a problem in that it takes time to confirm the establishment of synchronization.

In addition, when performing synchronization detection using synchronization words,
It is determined that synchronization has been established when synchronization words are detected consecutively, but in this type of system, it is necessary to consider situations such as incorrect detection or non-detection of synchronization words, so the external circuit becomes complicated. I had a problem with it.

The present invention has been made in view of the above-mentioned problems in the prior art, and its object is to provide a carrier lock detection circuit that can perform synchronization detection in a short time with a relatively simple circuit configuration.

[Means for Solving Problems] To achieve the above object, the present invention provides a carrier lock detection circuit for a demodulation circuit configured to establish synchronization by sweeping the frequency of an input modulation signal or a regenerated carrier wave. , an integrator that integrates and outputs the phase error signal detected and output from the demodulation circuit, and performs synchronization detection by comparing the output signal of this integrator with a preset threshold level, and directs the synchronization detection to the demodulation circuit. It includes a comparison circuit that outputs a signal, and is configured to stop the frequency sweep operation when the comparison circuit detects synchronization.

[Example] Next, a preferred example of the present invention will be described based on the drawings.

FIG. 1 shows a preferred example of a carrier lock detection circuit according to the present invention.

In the figure, 101 is a demodulation circuit having a frequency sweep function, and this demodulation circuit 101 includes a quadrature demodulator 102, a phase error detection circuit 103, a loop filter 105, an adder 106, and a VCO.
(voltage controlled oscillator) 104 and a control circuit 109.

As described above, the demodulator 10 having a frequency sweep function
1, it is necessary to take measures such as stopping the frequency sweep at the same time as synchronization is established as described above.

The feature of the present invention is that the carrier lock detection circuit
By using the integrator 107 and the comparator 108, synchronization detection can be performed in a short time with a relatively simple circuit configuration.

Here, the integrator 107 is formed to integrate and output the output of the phase error detection circuit 103. In other words, the frequency sweep in the demodulation circuit 101 is performed when the frequency fluctuation range of the input modulation signal exceeds the synchronizable range, but when this frequency sweep is performed, the phase error signal exceeds the synchronizable range. The beat signal becomes a beat signal according to the deviation frequency of the frequency fluctuation range. Therefore, a signal obtained by integrating a beat signal at a certain fixed time interval also becomes a beat signal, and its amplitude increases as the deviation frequency decreases.

Then, the signal integrated by the integrator 107 is output to the comparison circuit 108.

The comparison circuit 108 compares the output level of the integrator 107 with a preset threshold level, and uses the comparison results to determine whether the frequency sweep operation can be continued and whether the loop filter 105 can output the output. It is formed so as to be outputted to the control circuit 109 as a signal.

The present embodiment has the above configuration, and its operation will be explained next.

Note that since the demodulation circuit 101 is a well-known circuit, its operation will be briefly explained.

First, when a modulated wave signal is input to the demodulation circuit 101 via the input terminal 1, this modulated wave signal is input to the orthogonal demodulator 102.

The regenerated carrier wave output from the VCO 104 is also input to the orthogonal demodulator 102, and the modulated wave signal input from the input terminal 1 is orthogonally demodulated by this regenerated carrier wave, and is converted into an I signal which is a demodulated signal. It is output as a Q signal to output terminals 2 and 3 and to the phase error detection circuit 103.

At this time, if the frequency deviation between the input modulated wave signal and the reproduced carrier wave is within the lock range of the carrier wave recovery circuit, the reproduced carrier frequency can follow the input modulated wave frequency, and correct demodulation operation is performed.

However, if the frequency difference is not within the lock range, the correct demodulation operation is not performed and in this case a sweep command is applied to the input terminal 4. In response, control circuit 109 generates a frequency sweep signal and at the same time outputs a command signal to output 0 to loop filter 105.

This frequency sweep signal and the output of the loop filter 105 are added in an adder 106, and the VCO
Since the signal is output as a control voltage of 104, the frequency of the recovered carrier wave is swept.

On the other hand, the output of the phase error detection circuit 103 is 4Δf in 4-phase PSK, and 2-phase
In PSK, the beat signal has a frequency of 2Δf.

The process of forming this beat signal will be explained by taking the case of 4-phase PSK as an example with reference to FIG.

First, the phase error detection circuit 103 is, for example, of a Costas type, and its phase error detection characteristics are
As shown in Figure a, there are four phase lock points at ±45 degrees and ±135 degrees on the I-Q plane. In the figure, the polarity code "+" represents the leading phase control direction, and "-" represents the lagging phase control method. Then, when the input signal rotates clockwise at a speed of 2πΔft as shown in FIG. 2b, the output signal has a period Ts (Ts=1/
4Δf), resulting in a monotonically increasing signal.

If the regenerated carrier is frequency swept, Δf
will change, so the period of the output signal
Ts is also changing. From this, the output signal of the phase error detection circuit 103 becomes as shown in FIG. However, the figure shows the case where Δf is decreasing, and time t0 represents the point in time when Δf becomes 0.

The beat period t _b of the output of the phase error detection circuit is expressed by the following equation, where the frequency difference at that time is Δf.

t _b = π/2/Δf Therefore, when this output is integrated by the integrator 107 over the integration time Δt, the output becomes a beat signal when Δt>t _b and does not take a large value, but Δt When <t _b , it always has a constant polarity within the integration period, so it takes the maximum value.

Since the value of Δf decreases as the frequency is swept, at a certain point t _b >Δt, and the integrator output takes the maximum value. (See Figure 4) As the value of Δf, if the lock-in range of the carrier wave regenerator is f _R , it is sufficient to detect that Δf<f _R , so Δt>π/2/f _R. Just set it.

Therefore, as shown in FIG.
If the threshold value is set to 8, the threshold value will be exceeded when the output level Δf of the integrator 107 is near 0, so the output level of the comparator circuit 108 will be Δf approaches 0, as shown in FIG. and will change from low level to high level. In other words, it is possible to notify the control circuit 109 that Δf is near the lock point.

In this way, in the carrier lock detection circuit of this embodiment, the integrator 107 and the comparison circuit 108
Synchronization detection can be performed in a short time with a relatively simple configuration using

And when synchronization is detected in this way,
Since the control circuit 109 stops the frequency sweep operation and causes the loop filter 105 to start operating, the demodulation circuit 101 enters a normal synchronization state.

In this embodiment, the demodulation circuit 101 is of a type that sweeps the reproduced carrier wave, but the present invention is not limited to this. Needless to say, the present invention can be similarly applied to demodulation circuits.

Although one embodiment of the present invention has been described above,
The present invention is not limited to the above embodiments,
Various modifications can be made within the scope of the invention.

[Effects of the Invention] As explained above, according to the present invention, a relatively simple circuit configuration is provided in which the phase error detection signal detected by the demodulation circuit is integrated and the integrated value is compared with a predetermined threshold value. This has the effect of performing synchronization detection in a short time.

Further, according to the present invention, since the circuit configuration is relatively simple, the cost of the entire circuit can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram showing a preferred example of the carrier lock detection circuit and demodulation circuit according to the present invention, FIG. 2 is an explanatory diagram of the operation of the phase error detection circuit when the frequency difference Δf takes a finite value, and FIG. 4 is an output waveform diagram of the phase error detection circuit, FIG. 4 is an output waveform diagram of the integrator, and FIG. 5 is an explanatory diagram of the operation of the comparison circuit. 101: demodulation circuit, 103: phase error detection circuit, 107: integrator, 108: comparison circuit, 10
9: Control circuit.

Claims (1)

[Scope of Claims] 1. A carrier lock detection circuit for a demodulation circuit formed to establish synchronization by sweeping the frequency of an input modulation signal or a reproduced carrier wave, comprising: a phase error detected and output from the demodulation circuit; an integrator that integrates and outputs a signal; a comparison circuit that performs synchronization detection by comparing the output signal of the integrator with a preset threshold level and outputs a synchronization detection signal to a demodulation circuit; A carrier detection circuit characterized in that the comparison circuit is configured to stop frequency sweep operation when the comparison circuit detects synchronization.