JPH0115875B2 - - Google Patents

Description

[Detailed description of the invention]

``Industrial Application Field'' The present invention relates to a raster scan type cathode ray tube display device, and more particularly to a display device in which the brightness of displayed figures is made uniform. "Prior Art" As a display method in a refresh type cathode ray tube (hereinafter abbreviated as CRT) display device, a random scan type and a lantascan type are generally used. Although the random scan method has excellent definition of displayed figures, it is generally more expensive than the raster scan method, and has the disadvantage that flickering occurs when the number of display vectors increases. On the other hand, in the case of the raster scan method, the playback display is approximately
By using 30 screens, it is possible to obtain a stable screen without flickering, but especially when applied to a high-definition graphic display (for example, 1280 dots horizontally and 1024 dots vertically), the brightness of displayed figures may be affected. There is a problem that the values are not uniform. That is, in a high-definition (1280×1024 dots) graphic display, display methods for displaying each dot in the horizontal direction include a continuous display method and an intermittent display method. The continuous display method is a method in which when multiple dots to be displayed are consecutive, they are displayed by continuous pulse signals as shown in Figure 1A, and the intermittent display method is a method in which the dots are displayed as shown in Figure 1B. In this method, each dot is displayed using an intermittent pulse signal. In this case, if the intermittent display method is used, the brightness of the displayed figure will be uniform, but the video frequency will be approximately 52 MHz (in the case of a 1280 x 1024 dot graphic display), making video amplification technically difficult. On the other hand, in the case of continuous display, the video frequency is 26MHz, and video amplification is technically possible. Therefore, especially in high-definition graphic displays, it is necessary to adopt a continuous display method. "Problem to be solved by the invention" However, when a continuous display method is adopted,
This has the disadvantage that display strength (display brightness) varies. In other words, when displaying a single dot that is not continuous in the horizontal direction as shown in Figure 2A, the voltage applied to the CRT control grid may not reach the specified level due to the response speed of the video amplifier. , Therefore, sufficient display strength cannot be obtained. Further, as shown in FIG. 2B, when several dots are consecutive in the horizontal direction, the display is stronger than when a single dot is displayed, but sufficient display strength cannot yet be obtained. Further, when a large number of dots are continuous in the horizontal direction as shown in FIG. 2C, the output of the video amplifier reaches a specified level or higher, and sufficient display strength can be obtained. As a result, vectors in the horizontal direction are displayed more strongly than vectors in the vertical direction. In view of the circumstances described above, the present invention aims to equalize the display intensity in a high-definition raster scan type CRT display device. ``Means for Solving the Problems'' This invention provides calculation means for calculating the slope of a vector to be displayed from each Y and Z coordinate value of the start point and end point of the vector, and the slope calculated by the calculation means. is a plurality of predetermined tilt ranges, and belongs to one of at least a tilt range that includes the horizontal, a tilt range that includes the vertical, and one or more diagonal tilt ranges that do not include either the horizontal or the vertical. and outputting a weight bit that determines the level of the video signal for each tilt range so that the display brightness between the tilt ranges is substantially uniform, according to the determination result of the determination means. an image memory that stores dot data weighted according to the weight bits output from the data processing circuit; and a data processing circuit that reads out the weighted dot data in the image memory and processes each dot. The apparatus is equipped with video signal synthesis means for synthesizing video signals of a level corresponding to the weighting of data. "Embodiment" Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, the basic idea of this embodiment will be explained. As mentioned above, in the continuous display method, the horizontal vector VE ₁ (see Figure 3) is displayed most strongly, the vertical vector VE 2 is displayed somewhat weakly, and the vector VE ₂ in the direction 45° from the horizontal direction is displayed most strongly. VE ₃ , VE ₄ and the single dot D ₁ appear the weakest. Furthermore, if the length of the horizontal vector VE ₁ is short, it is displayed somewhat weakly. The reason why the vectors VE ₃ and VE ₄ in the 45° direction have the weakest display is that in the 45° direction, the dot spacing is the widest,
This is because it appears to be a weak display visually. Therefore, in this embodiment, first, the length and direction of the vector to be displayed are determined in a data processing circuit composed of a microcomputer, etc., and the display level (weight level) is calculated based on the result of this determination. . In this case, for example, as shown in Figure 4, the horizontal direction is 0°, and the direction of the vector is 0°~
Display level 1 is defined as between 30°, between 150° and 210°, and between 330° and 0° (inclination range including horizontal).
Also, if the direction of the vector is between 30° and 60°, and between 120° and
Between 150°, 210° to 240°, and 300° to 330° (diagonal tilt range that does not include horizontal or vertical) is set to display level 3, and between 60° and 120°, 240°. Display level 2 is between ~300° (tilt range including vertical).
Note that in this figure, point O is the starting point of the vector. Then, one of display levels 1 to 3 is assigned to the vector based on the direction and length of the vector determined by the data processing circuit. Regarding the determination of the length of a vector, for example, in the case of a single dot, level 3 is assigned. Also, for vectors with a length of 2 dots or more, first assign a level according to the direction, and only if the length is 2 dots, increase the level by one, and display level = display level determined by direction. +1. (However, if the display level determined by the direction is 3, the display level remains 3.) Next, the vector to which this display level is assigned is converted into bit data weighted according to the display level (hereinafter referred to as weight). (called bits). If display level 0 is no display, these display levels are represented by two weight bits. Then, a video signal is synthesized based on the weighted weight bits. In this case, display level 1
The video signal level corresponding to the weight bit of display level 2 is set as the reference level, the video signal level corresponding to the weight bit of display level 2 is set to be slightly higher than the reference level, and the video signal level corresponding to the weight bit of display level 3 is set to the highest level. level. In this manner, the display device according to the present invention attempts to equalize the display strength of each vector. Next, embodiments of the invention will be described. FIG. 5 is a block diagram showing the configuration of a high-definition (1280 x 1024 dots) display device according to the present invention. circuit 1, display controller 2, video amplifier 3, and CRT display device 4
It consists of Below, each of these parts will be explained in detail. First, the data processing circuit 1 includes a central processing unit (hereinafter abbreviated as CPU) 5, a program memory 6, and a graphic or vector memory connected to the CPU 5 via a bus line. 7 and an interface circuit 8. In this case, the program memory 6 stores a program that determines the direction and length of the vector to be displayed and calculates the display level based on the results of this determination, and the graphic or vector memory 7 stores data. Display commands supplied from outside the processing circuit 1 (not shown), coordinate data of vector starting points and ending points, etc. are recorded. and,
The CPU 5 determines the direction and length of the vector corresponding to the graphic data supplied from the graphic or vector memory 7 based on the program stored in the program memory 6, and sets display levels 1 to 3 based on the result of this determination. and weight bits b ₁ and b ₂ weighted as shown in Table 1 corresponding to the calculated display levels 1 to 3 are determined and output to the display controller 2 via the interface circuit 8. .

[Table] In Table 1, display level 0 indicates no display. Further, in this embodiment, the display level is determined based on FIG. 4, and the display level is determined in consideration of the length determination as described above. Next, the specific processing process of the CPU 5 will be described in the seventh section.
This will be explained with reference to the flowchart shown in the figure. First, in step S1, a display command in the memory 7 is read out, and it is deciphered whether the command is a command for instructing display or a command for instructing erasure of display. And if the command instructs to erase,
Proceeding to step S2, weight bits b ₁ and b ₂ are each set to (0, 0). If the command instructs display, the process advances to step S3. In step S3, the X, Y coordinate data of the starting point and the X, Y coordinate data of the ending point of the vector stored in the memory 7 are read out, and the respective X and Y coordinate data are compared. If the X-coordinate data of the starting point and the X-coordinate data of the ending point match, and the Y-coordinate data of the starting point and the Y-coordinate data of the ending point each match, that is, if what should be displayed is a single dot, the process advances to step S4. , set weight bits b ₁ and b ₂ to (1, 1) [display level 3]. Also, X
If one or both of the coordinate data and Y coordinate data do not match, the process advances to step S5. In step S5, △X = X coordinate data of the end point - X coordinate data of the start point △Y = Y coordinate data of the end point - Y coordinate data of the start point is calculated, and then △Y / △X is calculated. The slope tanθ of the vector can be found. Next, when the process advances to step S6, it is detected to which range of the slope range shown in FIG. 4 the slope of the vector belongs.
This detection is performed by checking whether the value of tanθ calculated in step S5 belongs to any of the following ranges. () −0.57735＜tanθ＜0.57735 () tanθ＞1.7325 or tanθ＜−1.7325 () 0.57735≦tanθ≦1.7325 or −1.7325≦tanθ≦−0.57735 In the above equation, −0.57735＝tan150゜＝tan330゜ 0. 57735=tan30゜= tan210° 1.7325 = tan60° = tan240° -1.7325 = tan120° = tan300°. Then, if the value of tanθ is within the range () above, proceed to step S7 and set the weight bit.
Set b ₁ and b ₂ to (0, 1) [display level 1],
If it is within the range of () above, proceed to step S8 and set weight bits b ₁ and b ₂ to (1, 0) [display level 2], and if it is within the range of () above, proceed to step S9. Go ahead, wait bit
Set b ₁ and b ₂ to (1, 1) [display level 3]. Next, in step S10, the number of display dots is calculated from the values of ΔX and ΔY. Next step
Proceeding to S11, it is determined whether the number of display dots calculated in step S10 is "2". In the case of "2", the process advances to step S12, and the display level "1" is added. However, this addition is not performed when the display level is "3". Above is the CPU
5 is the specific processing process. Next, the wait bits b ₁ and b ₂ output to the display controller 2 are supplied to the image memories 12 and 13, respectively, via the interface circuit 9, and the coordinate data of the starting point and ending point of the vector are also supplied to the interface circuit 9. The signal is supplied to the vector generation circuit 10 via the circuit 9. The image memories 12 and 13 each have a 1-bit storage location corresponding to each display dot on the display screen of the CRT display device 4,
Before starting display, all bits are first cleared. Note that this clearing is performed when wait bits b ₁ and b ₂ are in the state (0, 0) before the CPU 5 starts processing data in the graphic or vector memory 7. This is done by writing ₁ and b ₂ into the entire area of the image memories 12 and 13. The vector generation circuit 10 also receives the starting point of the vector supplied via the interface circuit 9;
Each coordinate of the end point is converted into the address of each dot for displaying the vector, and the vector is output sequentially. For example, if a certain vector is displayed by 10 dots, 10 data addresses indicating storage positions in the image memories 12 and 13 corresponding to the display position of each dot are output. Address control 11 is image memory 12, 13
This is a circuit that supplies write addresses and read addresses to. That is, this address control circuit 11
has a switching means for switching between a write address and a read address, and a read address signal generator,
When address data is supplied from the vector generation circuit 10, the same address data is sent to the image memories 12 and 13 via the switching means. As a result, the weight bits b ₁ and b ₂ output from the interface circuit 9 are written into the image memories 12 and 13, respectively. For example, suppose that the weight bits of a vector are (1, 0) and that vector is represented by 10 dots. In this case, vector generation circuit 10 to 10
Addresses are sequentially outputted and supplied to image memories 12 and 13 via address control circuit 11. As a result, "1" is written in each of the storage locations in the image memory 12 indicated by the above 10 addresses, and similarly, "0" is written in each of the storage locations in the image memory 13 indicated by the above 10 addresses. As described above, when the weight bits b ₁ and b ₂ and the start point/end point coordinates of a vector are output from the data processing circuit 1, the start point/end point coordinates of the vector are converted into address data, and the image indicated by the address data is converted. Wait bits b ₁ and b ₂ are written to storage locations in memories 12 and 13, respectively. In this process, the wait bits b ₁ , b ₂ are input from the data processing circuit 1.
and is performed every time the start point/end point coordinates of the vector are output. When the above processing is completed for all the vectors for one screen stored in the figure or vector memory 7, next, the image memories 12, 1
The data in 3 is read out and displayed. That is, the address control circuit 11 supplies a read address generated in an internal read address generation section to the image memories 12 and 13 based on a timing signal supplied from a timing controller (not shown). As a result, each weight bit in the image memories 12 and 13 becomes 1, for example.
The data is sequentially read out in byte (8 bit) units and supplied to the memory read circuit 14. Here, the above timing signal is a dot clock (CRT display device 4
This is a pulse signal with a frequency of 1/8 of the clock (which indicates the timing to display each dot). The memory readout circuit 14 is a type of buffer memory that temporarily stores the weight bits b ₁ and b ₂ read from the image memories 12 and 13 respectively, and serves as a parallel/serial conversion circuit (hereinafter abbreviated as P/S conversion circuit). Supply to 15. The P/S conversion circuit 15 is composed of a shift register, and converts the 8-bit equivalent wait bits b ₁ and b ₂ supplied from the memory read circuit 14 into serial wait bits b ₁ and b ₂ . The signal is supplied to the video synthesis circuit 16 at the timing of the dot clock. The video synthesis circuit 16 includes inverters 17 and 18, AND gates 19 to 22, variable resistors 23 to 26, and a resistor 27, and the P/S conversion circuit 15
The video signals of the levels corresponding to the weight bits b ₁ and b ₂ sequentially outputted from the video signals are synthesized and output to the video amplifier 3. In this case, variable resistor 23
26, only the output of AND gate 19 is at "H" level (AND gates 20 to 22).
When the output of the AND gate 20 is "L" level), the voltage P1 becomes "H" level, and when only the output of the AND gate 20 is "H" level, the voltage P2 becomes "H" level, only the output of the AND gate 21 becomes "H"
It is adjusted in advance so that the voltage is P3 when the output is at the "H" level, and the voltage P4 is when only the output of the AND gate 22 is at the "H" level. Here each voltage P1~P4
are the following voltages: P1<P2<P3<P4 Voltage P1 is the voltage at which no display occurs when the video signal is supplied to the CRT display device via the video amplifier 3. Voltage P2 is the voltage at which no display occurs when the video signal is supplied to the CRT display device via the video amplifier 3 When supplied to a display device, the voltage P3 displays three or more consecutive dots in the horizontal direction with appropriate brightness.When supplied as a video signal to a CRT display device via the video amplifier 3, the voltage P3 Voltage P4, which displays dots that are continuous in the horizontal direction with approximately the same brightness as three or more consecutive dots in the horizontal direction, is the voltage that displays dots that are continuous in the 45° direction when supplied to the CRT display device as a video signal via the video amplifier 3. _A voltage that displays consecutive dots in the horizontal direction with approximately the same brightness as three _or more consecutive dots in the horizontal direction. ”, only the output of the AND gate 19 becomes the “H” level, and the outputs of the other AND gates 20 to 22 all become the “L” level. As a result, the voltage obtained at point P shown in the figure becomes P1, and no dots are displayed on the CRT display device 4. Furthermore, when wait bits b ₁ and b ₂ are respectively "0, 1", only the output of AND gate 20 becomes "H" level, and the outputs of other AND gates 19, 21, 22 all become "L" level. becomes. As a result, the voltage obtained at point P becomes P2, and a dot display with a brightness corresponding to this voltage P2 is performed. Also, weight bit
If b ₁ and b ₂ are “1, 0” respectively, AND gate 2
Only the output of AND gate 1 becomes "H" level, and the outputs of other AND gates 19, 20, and 22 all become "L" level.
level. As a result, the voltage at point P becomes P3, and a dot display with a brightness corresponding to this voltage P3 is performed. Further, when wait bits b ₁ and b ₂ are respectively "1, 1", only the output of the AND gate 22 becomes "H" level, and the other AND gates 19 to
21 becomes the "L" level, and a dot display with a brightness corresponding to the voltage P4 is performed. As mentioned in Table 1 above, the combinations of the values of weight bits b ₁ and b ₂ correspond to display levels 1 to 3, respectively, so the values are long and continuous in the horizontal direction as shown in Figure 6A. In the case of dot display (display level 1), the voltage at point P is P2, and the voltage at the 6th point is P2.
As shown in Figure B, when short, continuous dots are displayed in the horizontal direction (display level 2), the voltage at point P is
P3, and when a single dot is displayed (display level 3) as shown in Figure 6 (c), the voltage at point P is
It becomes P4. As a result, the output signal of the video amplifier 3 is at substantially the same level at all display levels 1 to 3 (see FIG. 6), making it possible to make the display strength on the CRT display device 4 uniform. In the above-described embodiment, the number of weight bits is 2 bits, but by further increasing the number of weight bits, the display strength can be made more uniform.
For example, if the weight bit is 3 bits, the display strength can be controlled in 8 steps (however, 1 step is for no display).
This allows a more uniform screen to be obtained. "Effects of the Invention" As explained above, according to the present invention, the direction of the vector to be displayed is determined in advance, weight bits are determined based on the result of this determination, and a video signal is created based on the weight bits. As a result, in high-definition raster scan type CRT graphic displays, the input video signal frequency to the video amplifier can be uniformly distributed for each vector in the horizontal, vertical, and diagonal directions without increasing it beyond the technical limit. It is possible to achieve a screen with reduced display strength.

[Brief explanation of drawings]

Figures 1A and 2B are diagrams for explaining the continuous display method and intermittent display method in CRT display devices, respectively, and Figure 2 explains the reason why the display intensity is uneven in continuous display method CRT display devices. Figure 3 is a diagram showing an example of vectors displayed on a CRT screen, Figure 4 is a diagram showing classification of display levels, and Figure 5 is a block diagram showing the configuration of an embodiment of this invention. , FIG. 6 is a diagram for explaining the operation of the video synthesis circuit 16 in FIG. 5, and FIG. 7 is a flowchart showing the processing process of the CPU 5. 1... Data processing circuit, 12, 13... Image memory, 16... Video signal synthesis circuit.

Claims (1)

[Scope of Claims] 1. A raster scan type cathode ray tube display device, comprising: (a) calculation means for calculating the slope of a vector to be displayed from respective X and Y coordinate values of a starting point and an end point of the vector; and the calculation means; The calculated inclination thus falls within a plurality of predetermined inclination ranges, including at least a horizontal inclination range, a vertical inclination range, and one or more oblique ranges that do not include either the horizontal or the vertical. a determining means for determining which of the tilt ranges the video signal belongs to, and a weight bit for determining the level of the video signal for each tilt range so that the display brightness between the tilt ranges is approximately uniform; (b) an image memory for storing dot data weighted in accordance with weight bits output from the data processing circuit; (c) the image memory; 1. A display device comprising: video signal synthesis means for reading out weighted dot data within the dot data and synthesizing a video signal of a level corresponding to the weighting of each dot data.