JPH0115836B2 - - Google Patents
Info
- Publication number
- JPH0115836B2 JPH0115836B2 JP15125478A JP15125478A JPH0115836B2 JP H0115836 B2 JPH0115836 B2 JP H0115836B2 JP 15125478 A JP15125478 A JP 15125478A JP 15125478 A JP15125478 A JP 15125478A JP H0115836 B2 JPH0115836 B2 JP H0115836B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- alarm
- counter
- circuit
- volume
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000005236 sound signal Effects 0.000 claims description 12
- 239000013078 crystal Substances 0.000 claims description 7
- 230000010355 oscillation Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000000284 extract Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000010079 rubber tapping Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G04—HOROLOGY
- G04G—ELECTRONIC TIME-PIECES
- G04G13/00—Producing acoustic time signals
- G04G13/02—Producing acoustic time signals at preselected times, e.g. alarm clocks
- G04G13/021—Details
- G04G13/023—Adjusting the duration or amplitude of signals
Description
【発明の詳細な説明】
本発明は目覚音発生装置に関するものであり、
その目的とするところは、目覚まし音を一音づつ
小さな音量から徐々に大きくし、ある時間経過後
に小さな音量に復帰し、徐々に大きくなることを
繰返して快よさと確実な目覚まし機能を果すよう
な目覚音発生装置をきわめて安価な回路構成で提
供することにある。[Detailed description of the invention] The present invention relates to an alarm sound generating device,
The purpose of this is to gradually increase the alarm tone one tone at a time from a low volume, return to a low volume after a certain period of time, and repeat the process of gradually increasing the volume to provide a pleasant and reliable alarm function. An object of the present invention is to provide an alarm sound generating device with an extremely inexpensive circuit configuration.
従来の目覚音発生装置は、第１図のように、水
晶発振回路１の出力を分周回路２で分周してモー
タ駆動回路３によりモータ４を駆動して時計を形
成するとともに、分周回路２の２個所の所定段数
より取出した信号を目安スイツチ５とともに
NANDゲート６に入力し、報知器７を動作させ
て目覚まし音を報知していた。したがつて、目覚
まし音は一定音量を出力するだけにとどまり、動
作として単調であるという欠点を有していた。 As shown in FIG. 1, the conventional alarm sound generating device divides the output of a crystal oscillation circuit 1 by a frequency dividing circuit 2 and drives a motor 4 by a motor drive circuit 3 to form a clock. The signals extracted from two predetermined stages of circuit 2 are sent together with reference switch 5.
The signal was input to the NAND gate 6, and the alarm 7 was activated to notify the alarm sound. Therefore, the alarm tone has the disadvantage that it only outputs a constant volume and its operation is monotonous.
本発明はかかる点に鑑みて為されたものであ
り、本発明の目覚音発生装置は、水晶発振回路の
出力を分周回路で分周してモータ駆動用パルスと
し、分周回路の所定段より報知音信号を取り出し
て抵抗値の異なる複数の抵抗の並列回路を介して
報知器の音量制御端子に印加すると共に、前記分
周回路の後段より取り出した打音間隔決定パルス
信号を入力とするカウンタを設けて、前記カウン
タの各バイナリ信号がゲート開閉信号として一方
の入力端子に印加されるとともに他方の入力端子
に報知音信号が印加され上記各抵抗に対応して設
けられたANDゲートを、それぞれ上記各抵抗に
直列に挿入し、上記各抵抗の抵抗値を、カウンタ
のカウント値に応じて報知音量を徐々に大きくす
る音量制御信号が得られるように設定したもので
ある。 The present invention has been made in view of the above points, and the alarm sound generating device of the present invention divides the output of the crystal oscillation circuit by a frequency dividing circuit to generate motor driving pulses, and divides the output of the crystal oscillation circuit into a motor drive pulse, The notification sound signal is taken out from the above and applied to the volume control terminal of the alarm via a parallel circuit of a plurality of resistors having different resistance values, and the sound interval determining pulse signal taken out from the latter stage of the frequency dividing circuit is input. A counter is provided, each binary signal of the counter is applied as a gate opening/closing signal to one input terminal, and a notification sound signal is applied to the other input terminal, and an AND gate is provided corresponding to each of the resistors. Each of the resistors is inserted in series with each of the resistors, and the resistance value of each of the resistors is set so as to obtain a volume control signal that gradually increases the notification volume in accordance with the count value of the counter.
以下、本発明一実施例を図面を用いて説明す
る。 An embodiment of the present invention will be described below with reference to the drawings.
第２図において、１は水晶発振回路、２は分周
回路、３はモータ駆動回路、４はモータで、これ
らで時計を形成している。５は目安スイツチ、７
は報知器である。８は音量制御ゲート回路で、分
周回路２の所定段より報知音信号φ1を取出して
入力し、間欠的な報知音信号を出力して報知器７
より報知する。９は入力制御回路で、分周回路２
の後段より取出した打音間隔決定パルス信号と目
安スイツチ５の信号を入力し、その出力をカウン
タ１０に入力する。カウンタ１０のバイナリ信号
に従つて音量制御ゲート回路８を制御するように
しておく。 In FIG. 2, 1 is a crystal oscillation circuit, 2 is a frequency dividing circuit, 3 is a motor drive circuit, and 4 is a motor, which together form a clock. 5 is a guideline switch, 7
is an alarm. Reference numeral 8 denotes a volume control gate circuit, which extracts and inputs the notification sound signal φ 1 from a predetermined stage of the frequency dividing circuit 2, outputs an intermittent notification sound signal, and outputs an intermittent notification sound signal to the alarm 7.
Be more informed. 9 is an input control circuit, and frequency dividing circuit 2
The tapping interval determining pulse signal taken out from the latter stage and the signal from the reference switch 5 are input, and the output thereof is input to the counter 10. The volume control gate circuit 8 is controlled in accordance with the binary signal of the counter 10.
今、目安スイツチ５がオフのときは、カウンタ
１０はリセツト状態で、各ビツト出力がなく、音
量制御ゲート回路８のANDゲートAND1〜
AND4の出力はなく、報知器７は報知しない。つ
ぎに第３図の時刻t0で目安スイツチ５がオンする
と、カウンタ１０のリセツトがはずされ、同時に
入力制御回路９のANDゲートAND5から打音間
隔決定パルス信号φ2がカウンタ１０に入力する。
カウンタ１０にパルス信号が１個入力すると、
Q1からAND1へ“１”が入力して報知音信号φ1
が抵抗Raを介して報知器７へ入力されて報知さ
れる。このときの出力音量は抵抗Raによつて制
御される。これを出力１とする。つぎに、カウン
タ１０へパルス信号φ2が２個入力すると、Q1か
ら“０”、Q2から“１”が出力され、AND2より
報知音信号φ1が抵抗Rbによつて制御されて報知
器７より報知する。このとき、Ra＞Rbとすると
出力音量は出力１より大きくなり、出力２とす
る。カウンタ１０に３個入力するとQ1およびQ2
が“１”となり、AND1，AND2よりφ1が出力さ
れ、抵抗Raと抵抗Rbとが並列接続され（Ra
Rbと記す、以下同じ）、RaRbの抵抗値で出
力音量が制御される。ここで、Ra＞Rb＞（Ra
Rb）とすると出力音量は出力２より大きくな
る。ここで、ANDゲートが有する駆動力をそれ
ぞれの抵抗に加えて考慮する必要があるが、ここ
では省略して抵抗値のみで説明する。カウンタ１
０にパルス信号が４個入力すると、AND1，
AND2は閉じ、AND3のみから報知音信号φ1が抵
抗Rcによつて制御されて出力される。このとき
の出力を３とする。Ra＞Rb＞（RaRb）＞Rcと
すると、出力３は更に大きくなる。このようにし
てカウンタ１０の各ビツトが“1111”になるまで
出力音は増大する。このときの抵抗値は
Ra＞Rb（RaRb）＞Rc＞（RaRc）＞（Rb
Rc）＞（RaRbRc）＞Rd＞（RaRd）＞（Rb
Rd）＞（RaRbRd）＞（RcRd）＞（RaRc
Rd）＞（RbRcRd）＞（RaRbRcRd）
という条件を満す必要である。 Now, when the reference switch 5 is off, the counter 10 is in the reset state and there is no output of each bit, and the AND gate AND 1 ~ of the volume control gate circuit 8 is in the reset state.
There is no output of AND 4 , and the alarm 7 does not alarm. Next, when the reference switch 5 is turned on at time t0 in FIG. .
When one pulse signal is input to the counter 10,
“1” is input from Q 1 to AND 1 and notification sound signal φ 1
is input to the annunciator 7 via the resistor Ra and is notified. The output volume at this time is controlled by the resistor Ra. This is set as output 1. Next, when two pulse signals φ 2 are input to the counter 10, “0” is output from Q 1 , “1” is output from Q 2 , and the notification sound signal φ 1 is controlled by the resistor Rb from AND 2 . Announcement is made from the annunciator 7. At this time, if Ra>Rb, the output volume will be larger than output 1, and will be output 2. When 3 are input to counter 10, Q 1 and Q 2
becomes “1”, φ 1 is output from AND 1 and AND 2 , and resistor Ra and resistor Rb are connected in parallel (Ra
Rb (hereinafter the same), the output volume is controlled by the resistance value of RaRb. Here, Ra>Rb>(Ra
Rb), the output volume will be greater than output 2. Here, it is necessary to consider the driving force of the AND gate in addition to the respective resistances, but this will be omitted here and will be explained using only the resistance values. counter 1
When 4 pulse signals are input to 0, AND 1 ,
AND 2 is closed, and the notification sound signal φ 1 is output only from AND 3 under the control of resistor Rc. The output at this time is set to 3. When Ra>Rb>(RaRb)>Rc, the output 3 becomes even larger. In this way, the output sound increases until each bit of the counter 10 reaches "1111". The resistance value at this time is Ra>Rb(RaRb)>Rc>(RaRc)>(Rb
Rc)＞(RaRbRc)＞Rd＞(RaRd)＞(Rb
Rd)＞(RaRbRd)＞(RcRd)＞(RaRc
It is necessary to satisfy the following condition: Rd)>(RbRcRd)>(RaRbRcRd).
このようにして、カウンタ１０が“1111”のと
き最大音量となり、つぎにパルス信号φ2がカウ
ンタ１０に入力すると、“0000”になつてすべて
のANDゲートは閉じ、報知音はなくなり、つぎ
のパルス信号φ2がカウンタ１０に入力してQ1
“１”よりAND1が開き、抵抗Raによつて制御さ
れて出力音１となる。このようにして上記の出力
動作を繰返すことになる。この状態を第３図に図
示している。 In this way, when the counter 10 is "1111", the volume is at its maximum, and then when the pulse signal φ 2 is input to the counter 10, it becomes "0000", all the AND gates are closed, the notification sound disappears, and the next Pulse signal φ 2 is input to counter 10 and Q 1
AND 1 opens from "1", and the output sound is 1, which is controlled by the resistor Ra. In this way, the above output operation is repeated. This state is illustrated in FIG.
本発明は上述のように、水晶発振回路の出力を
分周回路で分周してモータ駆動用パルスとし、分
周回路の所定段より報知音信号を取り出して抵抗
値の異なる複数の抵抗の並列回路を介して報知器
の音量制御端子に印加すると共に、前記分周回路
の後段より取り出した打音間隔決定パルス信号を
入力とするカウンタを設けて、前記カウンタの各
バイナリ信号がゲート開閉信号として嘘一方の入
力端子に印加されるとともに他方の入力端子に報
知音信号が印加され上記各抵抗に対応して設けら
れたANDゲートを、それぞれ上記各抵抗に直列
に挿入し、上記各抵抗の抵抗値を、カウンタのカ
ウント値に応じて報知音量を徐々に大きくする音
量制御信号が得られるように設定したものである
ので、目覚まし音を一音づつ小さな音量から徐々
に大きくでき、ある時間経過後に小さな音量に復
帰し、徐々に大きくなることを繰返して快よい目
覚まし音とともに確実に目覚ましの機能を果すこ
とができる上に、報知音の変調回路をアナログス
イツチなどを使用せずに、カウンタとANDゲー
トの組み合わせによつてきわめて簡単且つ安価に
構成できるという効果を奏するものである。 As described above, the present invention divides the output of a crystal oscillator circuit using a frequency dividing circuit to generate pulses for driving a motor, extracts a notification sound signal from a predetermined stage of the frequency dividing circuit, and connects a plurality of resistors with different resistance values in parallel. A counter is provided which receives the sound interval determining pulse signal which is applied to the volume control terminal of the alarm via the circuit and which is also taken out from the latter stage of the frequency dividing circuit, and each binary signal of the counter is used as a gate opening/closing signal. A notification sound signal is applied to one input terminal and the other input terminal is applied.The AND gates provided corresponding to each of the above-mentioned resistors are inserted in series with each of the above-mentioned resistors, and the resistance of each of the above-mentioned resistors is The value is set to obtain a volume control signal that gradually increases the alarm volume according to the count value of the counter, so the alarm sound can be gradually increased from a low volume one sound at a time, and after a certain time elapses. Not only does it return to a low volume and then gradually increase in volume, it can reliably function as an alarm clock with a pleasant alarm sound. This has the effect of being extremely simple and inexpensive to configure by combining gates.
第１図は従来の目覚音発生装置の回路図、第２
図は本発明の一実施例の回路図、第３図ａ〜ｉは
同上の要部信号波形図である。
１……水晶発振回路、２……分周回路、３……
モータ駆動回路、４……モータ、５……目安スイ
ツチ、７……報知器、８……音量制御ゲート回
路、９……入力制御回路、１０……カウンタ。
Figure 1 is a circuit diagram of a conventional alarm sound generator, Figure 2 is a circuit diagram of a conventional alarm sound generator.
The figure is a circuit diagram of one embodiment of the present invention, and FIGS. 3a to 3i are main part signal waveform diagrams of the same. 1... Crystal oscillation circuit, 2... Frequency dividing circuit, 3...
Motor drive circuit, 4... Motor, 5... Reference switch, 7... Alarm, 8... Volume control gate circuit, 9... Input control circuit, 10... Counter.
Claims (1)
ータ駆動用パルスとし、分周回路の所定段より報
知音信号を取り出して抵抗値の異なる複数の抵抗
の並列回路を介して報知器の音量制御端子に印加
すると共に、前記分周回路の後段より取り出した
打音間隔決定パルス信号を入力とするカウンタを
設けて、前記カウンタの各バイナリ信号がゲート
開閉信号として一方の入力端子に印加されるとと
もに他方の入力端子に報知音信号が印加され上記
各抵抗に対応して設けられたANDゲートを、そ
れぞれ上記各抵抗に直列に挿入し、上記各抵抗の
抵抗値を、カウンタのカウント値に応じて報知音
量を徐々に大きくする音量制御信号が得られるよ
うに設定して成ることを特徴とする目覚音発生装
置。1 The output of the crystal oscillator circuit is frequency-divided by a frequency divider circuit to generate pulses for driving the motor, and the alarm sound signal is extracted from a predetermined stage of the frequency divider circuit and sent to the alarm signal through a parallel circuit of multiple resistors with different resistance values. A counter is provided which receives as input the sound interval determining pulse signal which is applied to the volume control terminal and which is taken out from the latter stage of the frequency dividing circuit, and each binary signal of the counter is applied to one input terminal as a gate opening/closing signal. At the same time, a notification sound signal is applied to the other input terminal, and the AND gates provided corresponding to each of the above-mentioned resistors are inserted in series with each of the above-mentioned resistors, and the resistance value of each of the above-mentioned resistors is set to the count value of the counter. An alarm sound generating device characterized in that it is configured to obtain a volume control signal that gradually increases a notification volume in accordance with the alarm volume.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15125478A JPS5576973A (en) | 1978-12-06 | 1978-12-06 | Alarm sound generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15125478A JPS5576973A (en) | 1978-12-06 | 1978-12-06 | Alarm sound generator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5576973A JPS5576973A (en) | 1980-06-10 |
| JPH0115836B2 true JPH0115836B2 (en) | 1989-03-20 |
Family
ID=15514634
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15125478A Granted JPS5576973A (en) | 1978-12-06 | 1978-12-06 | Alarm sound generator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5576973A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5793276A (en) * | 1980-12-02 | 1982-06-10 | Toshiba Corp | Electronic clock |
| JPS60238854A (en) * | 1984-05-11 | 1985-11-27 | Fuji Xerox Co Ltd | Alarm buzzer driving circuit of electronic copying machine |
-
1978
- 1978-12-06 JP JP15125478A patent/JPS5576973A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5576973A (en) | 1980-06-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1119024A (en) | Chime tone audio system utilizing a piezoelectric transducer | |
| US4573804A (en) | Scent-awake electronic clock | |
| JPH0115836B2 (en) | ||
| US5027686A (en) | Electronic metronome equipped with subtraction timer | |
| JPS5939713B2 (en) | alarm clock | |
| US4187670A (en) | Time signal generator circuit for use in an electronic timepiece | |
| JPS6038237Y2 (en) | Electronic clock with alarm | |
| JPS6156793B2 (en) | ||
| US4528681A (en) | Button depression click generator | |
| JPS6225747Y2 (en) | ||
| JPH0531590Y2 (en) | ||
| JPH0511516Y2 (en) | ||
| JPS6225748Y2 (en) | ||
| GB2027242A (en) | Improvements in or relating to alarm systems | |
| JPS5911119B2 (en) | electronic chime | |
| JPS6135991Y2 (en) | ||
| JPS624674B2 (en) | ||
| JPH0531588Y2 (en) | ||
| JPH0313756Y2 (en) | ||
| SU871144A2 (en) | Electronic timepiece | |
| JPH0373037U (en) | ||
| SU947952A2 (en) | Pulse duration discriminator | |
| JPH0216316Y2 (en) | ||
| JPS6122790B2 (en) | ||
| JPS6234315Y2 (en) |