JPH01154545A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH01154545A JPH01154545A JP62314635A JP31463587A JPH01154545A JP H01154545 A JPH01154545 A JP H01154545A JP 62314635 A JP62314635 A JP 62314635A JP 31463587 A JP31463587 A JP 31463587A JP H01154545 A JPH01154545 A JP H01154545A
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- hole
- intermediate plate
- resin
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 42
- 239000011347 resin Substances 0.000 claims abstract description 35
- 229920005989 resin Polymers 0.000 claims abstract description 35
- 238000007789 sealing Methods 0.000 abstract description 2
- 238000004806 packaging method and process Methods 0.000 abstract 6
- 238000012858 packaging process Methods 0.000 abstract 2
- 238000000034 method Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 241000587161 Gomphocarpus Species 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は樹脂封止型半導体装置に係り、特に、その外
装樹脂におけるクラック発生防止構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a resin-sealed semiconductor device, and particularly to a structure for preventing cracks in the exterior resin thereof.
従来から、この種の半導体装置として、第６図に示すよ
うな構造のものが知られている。この図において、符号
１０は半導体素子、１１は半導体素子１０がａｔ固定さ
れるダイパッド、１２はガル・ウィングといわれるタイ
プのり−ドビン、１３は半導体素子１０に配設された電
極とリードビン１２の内端部とを電気的に接続するワイ
ヤ、１４はリードピン１２の外端部を除く半導体装置の
要部を一体的に封止する外装樹脂である。Conventionally, as this type of semiconductor device, one having a structure as shown in FIG. 6 has been known. In this figure, reference numeral 10 denotes a semiconductor element, 11 a die pad to which the semiconductor element 10 is fixed, 12 a gull-wing type adhesive bin, and 13 an electrode and lead bin 12 arranged on the semiconductor element 10. The wire 14 that electrically connects the end of the lead pin 12 is an exterior resin that integrally seals the main parts of the semiconductor device except for the outer end of the lead pin 12.
ところで、前記構造の半導体装置においては、これを封
止する外装樹脂１４の有する線膨張係数が半導体素子工
０やダイパッド１１などの有する線膨張係数よりも大き
いため、つぎのような問題点があった。すなわち、この
半導体装置の全体がその実装プロセスにおいて加熱され
ると、前述したような線膨張係数の相違に基づき、既に
保管中における水分吸収などによって接着力が低下して
いたダイバノト１１の下面と外装樹脂１４の下側内面と
が、第７図に示すように互いに剥離してしまい、ダイパ
ッド１１の端部に内部応力が集中して外装樹脂１４にク
ラック１５が発生してしまうことになっていた。By the way, in the semiconductor device having the above structure, the coefficient of linear expansion of the exterior resin 14 that seals the device is larger than that of the semiconductor device 0, the die pad 11, etc., and therefore the following problems occur. Ta. In other words, when the entire semiconductor device is heated during the mounting process, due to the difference in linear expansion coefficient as described above, the lower surface and exterior of the divan board 11, whose adhesive strength has already been reduced due to moisture absorption during storage, etc. The lower inner surface of the resin 14 would peel off from each other as shown in FIG. 7, and internal stress would be concentrated at the end of the die pad 11, resulting in cracks 15 in the exterior resin 14. .
この発明は、このような問題点を解消するために創案さ
れたものであって、実装プロセスにおける加熱の際、半
導体装置の要部を封止する外装樹脂に発生するクラック
を有効に防止することが可能な半導体装置の提供を目的
としている。The present invention has been devised to solve these problems, and effectively prevents cracks from occurring in the exterior resin that seals the main parts of the semiconductor device during heating during the mounting process. The purpose is to provide a semiconductor device that is capable of
Ｃ問題点を解決するための手段〕
この発明においては、上記目的を達成するため、半導体
素子と、その裏面に接合された中間板と、この中間板を
介して前記半導体素子を固定支持するダイパッドと、こ
れらを封止する外袋樹脂とを備え、前記ダイパッドには
その表裏に開口するダイパッド貫通孔を形成するととも
に、前記中間板には前記ダイパッド貫通孔に連通し、か
つ、これよりも大きな開口面積を存する中間板貫通孔を
形成し、さらに、この中間板貫通孔および前記ダイパッ
ド貫通孔の内部に前記外装樹脂の一部を充填した構成に
特徴を有するものである。Means for Solving Problem C] In order to achieve the above object, the present invention includes a semiconductor element, an intermediate plate bonded to the back surface of the semiconductor element, and a die pad that fixedly supports the semiconductor element via the intermediate plate. and an outer bag resin for sealing these, the die pad has a die pad through hole that opens on the front and back sides thereof, and the intermediate plate has a die pad through hole that is connected to the die pad through hole and is larger than the die pad through hole. The present invention is characterized in that an intermediate plate through hole having an opening area is formed, and a portion of the exterior resin is filled inside the intermediate plate through hole and the die pad through hole.
上記構成によれば、半導体装置の要部を封止する外装樹
脂の一部がダイパッド貫通孔を通過して半導体素子の裏
面に接合された中間板の中間板貫通孔の内部にまで充填
されることにより、中間板貫通孔内の樹脂がダイパッド
貫通孔周囲のダイパッド上面に係合しているので、ダイ
パッドと中間板とが外装樹脂の一部を介して互いに機械
的に固定支持されていることになる。According to the above configuration, a part of the exterior resin that seals the main parts of the semiconductor device passes through the die pad through hole and is filled into the intermediate plate through hole of the intermediate plate bonded to the back surface of the semiconductor element. As a result, the resin in the intermediate plate through-hole engages with the upper surface of the die pad around the die pad through-hole, so that the die pad and the intermediate plate are mechanically fixed and supported to each other via a part of the exterior resin. become.
したがって、半導体装置が全体的に加熱されても、ダイ
パッドと中間板とがそれぞれの有する線膨張係数の相違
によって剥離することがなく、このような剥離に伴う内
部応力がダイパッドの端部に集中して外装樹脂にクラッ
クが発生することが有効に防止される。Therefore, even if the semiconductor device is heated as a whole, the die pad and the intermediate plate will not separate due to the difference in their linear expansion coefficients, and the internal stress caused by such separation will be concentrated at the end of the die pad. This effectively prevents cracks from occurring in the exterior resin.
以下、この発明に係る一実施例を図面に基づいて説明す
る。Hereinafter, one embodiment of the present invention will be described based on the drawings.
第１図は本発明に係る樹脂封止型半導体装置の概略構造
を示す断面図であって、この図における符号１は半導体
素子、２は半導体素子１の裏面に接合された中間板、３
は中間板２を介して半導体素子１を固定支持するダイパ
ッドである。そして、第２図の平面図に示すような平面
視略矩形状の金属平板からなるダイパッド３の略中央位
置には、その表裏に開口する円形状のダイパッド貫通孔
３ａが形成されている。また、第３図の平面図に示すよ
うに、このダイパッド３と前記半導体素子ｌとの間に介
装された中間板２もダイパッド３と略同形状の金属平板
からなり、その略中央位置にはダイパッド貫通孔３ａに
連通ずるとともに、これよりも大きな開口面積を有する
円形状の中間板貫通孔２ａが形成されている。FIG. 1 is a sectional view showing a schematic structure of a resin-sealed semiconductor device according to the present invention, in which reference numeral 1 denotes a semiconductor element, 2 an intermediate plate bonded to the back surface of the semiconductor element 1, and 3
is a die pad that fixedly supports the semiconductor element 1 via the intermediate plate 2. A circular die pad through-hole 3a is formed at the approximate center of the die pad 3, which is a metal flat plate having a substantially rectangular shape in a plan view as shown in the plan view of FIG. Further, as shown in the plan view of FIG. 3, the intermediate plate 2 interposed between the die pad 3 and the semiconductor element 1 is also made of a flat metal plate having approximately the same shape as the die pad 3, and is located approximately at the center of the intermediate plate 2. A circular intermediate plate through hole 2a is formed which communicates with the die pad through hole 3a and has a larger opening area than the die pad through hole 3a.
一方、前記ダイパッド２の周囲には、ガル・ウィングタ
イプとされた複数のり−ドピン４が並列配置されており
、リードピン４の内端部と半導体素子１に配設された電
極とは、互いにワイヤ５を介して電気的に接続されてい
る。そして、リードビン４の外端部を除く全ての部品、
すなわち、半導体装置の要部は外装樹脂６によって一体
的に封止されており、前記中間板貫通孔２ａおよびダイ
パッド貫通孔３ａの内部それぞれには外装樹脂６の一部
が充填されている。したがって、ダイパッド貫通孔３ａ
を通過して、いわゆる「釘の頭」状で中間板貫通孔２ａ
内に充填された外装樹脂６の一部はダイパッド３のグイ
パッド貫通孔３ａ周囲の上面に係合することになり、こ
のダイパッド３と中間板２とは互いに外装樹脂６の一部
を介して互いに機械的に固定支持されていることになる
。On the other hand, a plurality of gull-wing type lead pins 4 are arranged in parallel around the die pad 2, and the inner ends of the lead pins 4 and the electrodes arranged on the semiconductor element 1 are connected to each other by wires. They are electrically connected via 5. All parts except the outer end of the lead bin 4,
That is, the main parts of the semiconductor device are integrally sealed with the exterior resin 6, and a portion of the exterior resin 6 is filled inside each of the intermediate plate through hole 2a and the die pad through hole 3a. Therefore, the die pad through hole 3a
through the intermediate plate through hole 2a in the shape of a so-called "nail head".
A part of the exterior resin 6 filled therein will engage with the upper surface around the guide pad through hole 3a of the die pad 3, and the die pad 3 and the intermediate plate 2 are connected to each other through a part of the exterior resin 6. It is mechanically fixedly supported.
そのため、上記構造によれば、この半導体装置が実装プ
ロセスにおいて加熱されても、そのグイパット３の下面
と外装樹脂６の下側内面とが、中間板貫通孔２ａおよび
ダイパッド貫通孔３ａの内部に充填された外装樹脂６の
一部によって固持されることになり、従来例のように、
これらがＩ’？！Ｉ 離してしまうことがないので、こ
のような剥離に伴う内部応力がダイパッド３の端部に集
中して外装樹脂６にクランクが発生することはない。Therefore, according to the above structure, even if this semiconductor device is heated during the mounting process, the lower surface of the gui pad 3 and the lower inner surface of the exterior resin 6 fill the inside of the intermediate plate through hole 2a and the die pad through hole 3a. It will be held firmly by a part of the exterior resin 6 that has been removed, and as in the conventional example,
Are these I'? ! Since the peeling does not occur, the internal stress caused by such peeling does not concentrate on the ends of the die pad 3 and cause cranking in the exterior resin 6.
なお、以上の説明においては、半導体装置を構成する中
間板２およびダイパッド３それぞれの互いに対応する位
置に、円形状で単一の貫通孔２ａ。In the above description, a single circular through hole 2a is provided at corresponding positions in the intermediate plate 2 and the die pad 3 that constitute the semiconductor device.
３ａを設けるものとして説明したが、本発明はこれに限
定されるものではなく、例えば、他の実施例として、第
４図の断面図および第５０の平面図に示すように、中間
板２に略矩形状の中間板貫通孔２ｂを形成するとともに
、ダイバット３に複数のダイパッド貫通孔３ｂ、・・・
を設けておいてもよい。また、本実施例の半導体装置に
おいては、そのリードピン４の形状をガル・ウィングタ
イプとして説明しているが、例えば、Ｊ・リードタイプ
などのり−ドピンであっても同様に構成できることはい
うまでもない。3a, the present invention is not limited to this. For example, as another embodiment, as shown in the sectional view of FIG. 4 and the 50th plan view, the intermediate plate 2 is provided with a A substantially rectangular intermediate plate through hole 2b is formed, and a plurality of die pad through holes 3b, . . . are formed in the die butt 3.
may be provided. Further, in the semiconductor device of this embodiment, the shape of the lead pin 4 is described as a gull-wing type, but it goes without saying that it can be constructed in the same manner even if it is a glue-doped pin such as a J-lead type. do not have.
以上説明したように、この発明によれば、半導体装置の
要部を封止する外装樹脂の一部がダイパッド貫通孔を通
過して半導体素子の裏面に接合された中間板の中間板貫
通孔の内部にまで充填され、この中間板貫通孔内の樹脂
がダイパッド貫通孔周囲のダイパッド上面に係合するこ
とによってダイパッドと中間板とが外装樹脂の一部を介
して互いに機械的に固定支持されることになる。したが
って、半導体装置が全体的に加熱されても、従来例のよ
うに、ダイパッドと中間板とがそれぞれの有する線膨張
係数の相違によって？Ｌ１１離することがなく、このよ
うな剥離に伴う内部応力がダイパッドの端部に集中して
外装樹脂にクラックが発生することが有効に防止される
という効果がある。As explained above, according to the present invention, a part of the exterior resin that seals the main parts of the semiconductor device passes through the die pad through hole and is inserted into the intermediate plate through hole of the intermediate plate bonded to the back surface of the semiconductor element. The resin in the intermediate plate through hole engages with the upper surface of the die pad around the die pad through hole, whereby the die pad and the intermediate plate are mechanically fixed and supported to each other via a part of the exterior resin. It turns out. Therefore, even if the semiconductor device is heated as a whole, as in the conventional example, is it due to the difference in linear expansion coefficient between the die pad and the intermediate plate? L11 does not separate, and the internal stress caused by such peeling is concentrated at the end of the die pad, effectively preventing cracks from occurring in the exterior resin.
第１図ないし第５図は本発明の実施例に係り、第１図は
本発明の一実施例に係る半導体装置の概略構造を示す断
面図、第２図はその中間板の平面図、第３図はそのダイ
パッドの平面図であり、第４図は他の実施例に係る半導
体装置の概略構造を示す断面図、第５図はその中間板の
平面図である。
また、第６図および第７図は従来例に係り、第６図は半
導体装置の概略構造を示す断面図、第７図はその要部を
封止する外装樹脂にクラックが発生した状態を示す断面
図である。
図において、１は半導体素子、２は中間板、２ａ、２ｂ
は中間板貫通孔、３はダイパッド、３ａ。
３ｂはダイパッド貫通孔、６は外装樹脂である。1 to 5 relate to embodiments of the present invention, in which FIG. 1 is a sectional view showing a schematic structure of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a plan view of an intermediate plate thereof, and FIG. 3 is a plan view of the die pad, FIG. 4 is a sectional view showing the schematic structure of a semiconductor device according to another embodiment, and FIG. 5 is a plan view of the intermediate plate thereof. Furthermore, FIGS. 6 and 7 relate to conventional examples, where FIG. 6 is a cross-sectional view showing the schematic structure of a semiconductor device, and FIG. 7 shows a state in which cracks have occurred in the exterior resin that seals the main parts of the device. FIG. In the figure, 1 is a semiconductor element, 2 is an intermediate plate, 2a, 2b
3 is an intermediate plate through hole, 3 is a die pad, and 3a. 3b is a die pad through hole, and 6 is an exterior resin.
Claims (1)
この中間板を介して前記半導体素子を固定支持するダイ
パッドと、これらを封止する外装樹脂とを備え、 前記ダイパッドには、その表裏に開口するダイパッド貫
通孔を形成するとともに、 前記中間板には、前記ダイパッド貫通孔に連通し、かつ
、これよりも大きな開口面積を有する中間板貫通孔を形
成し、 さらに、この中間板貫通孔および前記ダイパッド貫通孔
の内部に、前記外装樹脂の一部を充填したことを特徴と
する樹脂封止型半導体装置。(1) A semiconductor element, an intermediate plate bonded to the back surface of the semiconductor element,
A die pad that fixedly supports the semiconductor element via the intermediate plate and an exterior resin that seals these are provided, and the die pad is provided with a die pad through hole that opens on the front and back sides thereof, and the intermediate plate includes: , an intermediate plate through hole communicating with the die pad through hole and having a larger opening area than the intermediate plate through hole is formed, and further, a part of the exterior resin is placed inside the intermediate plate through hole and the die pad through hole. A resin-sealed semiconductor device characterized by being filled.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62314635A JP2536564B2 (en) | 1987-12-10 | 1987-12-10 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62314635A JP2536564B2 (en) | 1987-12-10 | 1987-12-10 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01154545A true JPH01154545A (en) | 1989-06-16 |
| JP2536564B2 JP2536564B2 (en) | 1996-09-18 |
Family
ID=18055692
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62314635A Expired - Lifetime JP2536564B2 (en) | 1987-12-10 | 1987-12-10 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2536564B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05243469A (en) * | 1992-02-28 | 1993-09-21 | Nec Kyushu Ltd | Lead frame for semiconductor device |
| US5264730A (en) * | 1990-01-06 | 1993-11-23 | Fujitsu Limited | Resin mold package structure of integrated circuit |
| US5367191A (en) * | 1991-09-18 | 1994-11-22 | Fujitsu Limited | Leadframe and resin-sealed semiconductor device |
| JP2008254445A (en) * | 2007-03-30 | 2008-10-23 | Wc Heraeus Gmbh | System carrier strip for electronic constituent element |
-
1987
- 1987-12-10 JP JP62314635A patent/JP2536564B2/en not_active Expired - Lifetime
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5264730A (en) * | 1990-01-06 | 1993-11-23 | Fujitsu Limited | Resin mold package structure of integrated circuit |
| US5367191A (en) * | 1991-09-18 | 1994-11-22 | Fujitsu Limited | Leadframe and resin-sealed semiconductor device |
| US5753535A (en) * | 1991-09-18 | 1998-05-19 | Fujitsu Limited | Leadframe and resin-sealed semiconductor device |
| JPH05243469A (en) * | 1992-02-28 | 1993-09-21 | Nec Kyushu Ltd | Lead frame for semiconductor device |
| JP2008254445A (en) * | 2007-03-30 | 2008-10-23 | Wc Heraeus Gmbh | System carrier strip for electronic constituent element |
| EP1976006A3 (en) * | 2007-03-30 | 2008-11-05 | W.C. Heraeus GmbH | System carrier tape for electronic components |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2536564B2 (en) | 1996-09-18 |
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