JPH01152668A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01152668A JPH01152668A JP31130587A JP31130587A JPH01152668A JP H01152668 A JPH01152668 A JP H01152668A JP 31130587 A JP31130587 A JP 31130587A JP 31130587 A JP31130587 A JP 31130587A JP H01152668 A JPH01152668 A JP H01152668A
- Authority
- JP
- Japan
- Prior art keywords
- materials
- passivation
- semiconductor substrate
- mold
- silicone rubber
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 239000000463 material Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000002161 passivation Methods 0.000 claims abstract description 25
- 230000001681 protective effect Effects 0.000 claims abstract description 14
- 239000011248 coating agent Substances 0.000 claims description 3
- 238000000576 coating method Methods 0.000 claims description 3
- 238000007711 solidification Methods 0.000 claims 1
- 230000008023 solidification Effects 0.000 claims 1
- 229920002379 silicone rubber Polymers 0.000 abstract description 9
- 239000004945 silicone rubber Substances 0.000 abstract description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 230000015556 catabolic process Effects 0.000 abstract description 4
- 238000001035 drying Methods 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 abstract 1
- 229910052731 fluorine Inorganic materials 0.000 abstract 1
- 239000011737 fluorine Substances 0.000 abstract 1
- 239000012299 nitrogen atmosphere Substances 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 239000011347 resin Substances 0.000 abstract 1
- 229920005989 resin Polymers 0.000 abstract 1
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 238000005266 casting Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000001105 regulatory effect Effects 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000003672 processing method Methods 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 238000009864 tensile test Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66363—Thyristors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/74—Thyristor-type devices, e.g. having four-zone regenerative action
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体基板が交互に異なる導電型をもって隣
接する層を３層以上有し、一つの低不純物濃度層と隣接
する二つの異なる導電型の層との間のＰＮ接合に対して
それぞれ正ベベル形状が作成されるいわゆるシグマ （
Σ）ベベル構造を有するサイリスタなどの半導体装置の
製造方法に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a semiconductor substrate having three or more adjacent layers having alternately different conductivity types, one low impurity concentration layer and two adjacent layers of different conductivity. The so-called sigma (
Σ) A method of manufacturing a semiconductor device such as a thyristor having a bevel structure.
高耐圧化のために第２図のようなΣベベル構造を有する
サイリスタが知られている。すなわち、ｐエミッタ層１
１． Ｎベース層１２．Ｐベース層１３゜Ｎエミツタ
層１４からなるシリコン基板ｌがアノード電極板２の上
に支持され、Ｎエミツタ層１４にはカソード電極３が設
けられて半導体基体が形成されているが、半導体基板１
の側面はＮベース層１２が最も小さい断面積となってお
り、ｐエミッタ層１１とＮベース層１２の間、Ｎベース
層１２とＰベース層１３の間の双方のＰＮ接合に対し、
Ａベル形状となっている。このようなベベル形状は、サ
ンドブラストなどのシリコン加工法によって形成され、
次いでベベル部は、例えば弗酸・硝酸系のエツチング液
でエツチングされる。その後、表面安定化のために、例
えばシリコンゴムなどでベベル面を被覆してパンシベー
シッンが行われる。A thyristor having a Σ bevel structure as shown in FIG. 2 is known for achieving high voltage resistance. That is, p emitter layer 1
1. N base layer 12. A silicon substrate 1 consisting of a P base layer 13° and an N emitter layer 14 is supported on an anode electrode plate 2, and a cathode electrode 3 is provided on the N emitter layer 14 to form a semiconductor substrate.
The side surface of the N base layer 12 has the smallest cross-sectional area, and for both the PN junctions between the P emitter layer 11 and the N base layer 12 and between the N base layer 12 and the P base layer 13,
It has an A-bell shape. This beveled shape is formed by silicon processing methods such as sandblasting,
Next, the bevel portion is etched using, for example, a hydrofluoric acid/nitric acid based etching solution. Thereafter, in order to stabilize the surface, the beveled surface is coated with, for example, silicone rubber, and pansibasing is performed.
シカシ、第３図に示すようにパンシベーシッン材４で被
覆する際、Σベベルの上部エツジ部１５の上のパッシベ
ーション膜が薄くなったり、あるいはエツジ部が露出す
るため、電圧印加したとき非常に放電しやすくなる。ま
た機械的応力が上部エツジ部１５にかかったとき、エツ
ジ部に欠けが生じ、耐圧劣化が起こるという問題があっ
た。As shown in Fig. 3, when covering with the pansibasin material 4, the passivation film on the upper edge part 15 of the Σ bevel becomes thinner or the edge part is exposed, resulting in a severe discharge when voltage is applied. It becomes easier. Further, when mechanical stress is applied to the upper edge portion 15, there is a problem in that the edge portion is chipped and the pressure resistance deteriorates.
本発明の目的は、エツジ部に起こるパッシベーションの
弱点あるいは欠けなどがなく、耐圧特性が安定で、信頼
性の高い半導体装置の製造方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device that is free from passivation weaknesses or chips that occur in edge portions, has stable breakdown voltage characteristics, and is highly reliable.
上記の目的を達成するために、本発明は、半導体基体の
半導体基板の側面にΣベベル形状を有し、少なくとも一
方のベベル末端のエツジ部がパッシベーション材で覆わ
れる半導体装置の製造に際し、パッシベーション材を被
覆後、半導体基体を半導体基板面に垂直な側壁をもつ型
の中に入れ、絶縁性保護材を半導体基体周囲の空間に注
入固化したのち型を取外すものとする。In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor device in which a side surface of a semiconductor substrate of a semiconductor substrate has a Σ bevel shape, and an edge portion of at least one end of the bevel is covered with a passivation material. After coating, the semiconductor substrate is placed in a mold having side walls perpendicular to the surface of the semiconductor substrate, and after the insulating protective material is injected into the space around the semiconductor substrate and solidified, the mold is removed.
型と半導体基体周囲の空間に注型された絶縁性材料カニ
ベベル構造のエツジ部を保護し、エツジ部上のパッシベ
ーション材の薄い部分またはない部分への被覆あるいは
欠けの防止などの役目をする。It protects the edges of the insulating material crab bevel structure cast in the space around the mold and semiconductor substrate, and serves to cover thin or non-existent parts of the passivation material on the edges and prevent chipping.
本発明の一実施例を第１図（ａ）〜（Ｃ１により説明す
る。Σベベルのエツチング処理まで終了した半導体基板
１の露出面にＮ、雰囲気のクリーンボックス内で、例え
ばはけなどを用いてシリコンゴムなどのパッシベーショ
ン材４を塗布する。乾燥後パッシベーション部は第１図
ｆａｔで示す形状となる。An embodiment of the present invention will be explained with reference to FIGS. 1(a) to (C1). The exposed surface of the semiconductor substrate 1, which has been etched to the Σ bevel, is etched using a brush or the like in a clean box with N atmosphere. Then, a passivation material 4 such as silicone rubber is applied.After drying, the passivation part takes the shape shown by fat in FIG.
次に、第１図（ｂｌに示すように、例えば商品名テフロ
ンなどのふっ素樹脂からなる型６で電極２゜３を備えた
半導体基板１の周辺を囲み、パッシベーション材４を被
覆した半導体基板１と型６との間に、さらにシリコンゴ
ムなどの絶縁性保護材５を流しこむ、乾燥後型を取外す
。型６は、十分脱脂、洗浄されたもので、また保護材５
に不溶で剥離性の良いものであることはいうまでもない
。Next, as shown in FIG. 1 (bl), a mold 6 made of a fluororesin such as Teflon (trade name) is used to surround the semiconductor substrate 1 provided with the electrodes 2.3, and the semiconductor substrate 1 is coated with a passivation material 4. An insulating protective material 5 such as silicone rubber is poured between the mold 6 and the mold 6, and the mold is removed after drying.The mold 6 is thoroughly degreased and cleaned, and the protective material 5 is
Needless to say, it is insoluble in water and has good removability.
型を外した後の状態を第１図ｆｃｌに示す、パッシベー
ション材４は、例えばはけなどを用いた塗布をするため
、シリコン基板１との間に空洞は生じない、また、−度
乾燥させたパッシベーション材４の上に保護材５を注型
するが、その界面にも空洞は生じなく、また保護材５に
パッシベーション材４に同じ材料、例えばシリコンゴム
を使えば、保護材５の強度はパッシベーション材の強度
に劣らないことがわかっている。これは、上記と同一条
件にて試料を作成し、ＪＩＳ規格の引張り試験を行った
ところ、最大荷重２５ｋｇで一層目のシリコンゴムとシ
リコン材との間に剥離が生じ、重ねられた一層目と二層
目のシリコンゴムの界面では剥離が生じなかったことに
よる。The state after removing the mold is shown in FIG. The protective material 5 is cast on the passivation material 4, but no cavities are formed at the interface.If the same material as the passivation material 4, for example silicone rubber, is used for the protective material 5, the strength of the protective material 5 will be It is known that the strength is not inferior to that of passivation materials. When a sample was prepared under the same conditions as above and subjected to a tensile test according to the JIS standard, peeling occurred between the first layer of silicone rubber and the silicone material at a maximum load of 25 kg. This is because no peeling occurred at the interface of the second layer of silicone rubber.
このようなシリコン基板１および電極２．３からなる半
導体基体を第４図に示すように、内部電極体７と共に二
つの外部電極体２１．２２がセラミ・ンク側壁２３とフ
ランジ２４を介して結合される容器内に組込むときには
、注型保護材５が側壁２３の内面を案内面として基体の
位置を中央に規制する働きを兼ねる。従つて第５図に示
した弧状体の中央（立置規制部材２５を特に準備する必
要はなく、半導体装置の部品域になる。As shown in FIG. 4, a semiconductor body consisting of such a silicon substrate 1 and an electrode 2.3 is connected to an internal electrode body 7 and two external electrode bodies 21, 22 via a ceramic ink side wall 23 and a flange 24. When the base body is assembled into a container, the casting protection member 5 also functions to regulate the position of the base body to the center by using the inner surface of the side wall 23 as a guide surface. Therefore, there is no need to prepare the vertical position regulating member 25 at the center of the arc-shaped body shown in FIG. 5, and this becomes the component area of the semiconductor device.
保護材５としてパッシベーション材４と同一材料を用い
ることは、例えばエツジ部において半導体基板１の露出
の場合のパッシベーションの補償あるいは、パッシベー
ション材と保護材の強い密着性などの点で有利であるが
、必ずしも同一材料でなくてもよい。Using the same material as the passivation material 4 as the protective material 5 is advantageous in terms of compensating for passivation when the semiconductor substrate 1 is exposed at the edge portion, for example, or in ensuring strong adhesion between the passivation material and the protective material. They do not necessarily have to be made of the same material.
本発明によれば、Σベベル構造での外周へ突出するエツ
ジ部を保護する材料をパッシベーション材被覆に注型す
ることにより、エツジ部のパッシベーション弱点の補強
や機械的な強化を行うことができ、エツジ部におけるパ
ッシベーション不足による放電や、かけ発生による耐圧
劣化がなくなり、Σベベル構造をもつ半導体装置の耐圧
特性の安定化および信頼性の向上に有効である。併せて
保護材が半導体基体の中央位置規制部材を兼ねる効果も
得られる。According to the present invention, by casting a material that protects the edge portion protruding to the outer periphery of the Σ bevel structure into the passivation material coating, it is possible to reinforce the passivation weak point of the edge portion and mechanically strengthen it. This eliminates discharge due to lack of passivation in the edge portion and deterioration of breakdown voltage due to chipping, and is effective in stabilizing breakdown voltage characteristics and improving reliability of a semiconductor device having a Σ bevel structure. In addition, the protective material also serves as a central position regulating member of the semiconductor substrate.
第１図（ａｌ〜ｆｃｌは本発明の一実施例の工程を示す
断面図、第２図はΣベベル構造をもつ半導体基体の断面
図、第３図は第２図に示した半導体基体へのパッシベー
ション後の断面図、第４図は本発明の一実施例による半
導体基体を用いた半導体装置の断面図、第５図は従来の
半導体装置の断面図である。
１：シリコン基板、２ニアノード電極板、３：カソード
電極、４：パッシベーション材、５：保護材。
第１図FIG. 1 (al to fcl are cross-sectional views showing the steps of an embodiment of the present invention, FIG. 2 is a cross-sectional view of a semiconductor substrate having a Σ bevel structure, and FIG. 3 is a cross-sectional view of a semiconductor substrate shown in FIG. 2). 4 is a sectional view of a semiconductor device using a semiconductor substrate according to an embodiment of the present invention, and FIG. 5 is a sectional view of a conventional semiconductor device. 1: Silicon substrate, 2 Near anode electrode. Plate, 3: cathode electrode, 4: passivation material, 5: protective material. Figure 1
Claims (1)
状を有し、少なくとも一方のベベル末端のエッジ部がパ
ッシベーション材で覆われる半導体装置の製造の際に、
パッシベーション材を被覆後半導体基体の半導体基板面
に垂直な側壁をもつ型の中に入れ、絶縁性保護材を半導
体基体周囲の空間に注入し、固化したのち型を取外すこ
とを特徴とする半導体装置の製造方法。(1) When manufacturing a semiconductor device in which the side surface of the semiconductor substrate of the semiconductor substrate has a sigma bevel shape, and at least one end edge of the bevel is covered with a passivation material,
A semiconductor device characterized in that after coating a passivation material, a semiconductor substrate is placed in a mold having side walls perpendicular to the semiconductor substrate surface, an insulating protective material is injected into the space around the semiconductor substrate, and the mold is removed after solidification. manufacturing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31130587A JPH01152668A (en) | 1987-12-09 | 1987-12-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31130587A JPH01152668A (en) | 1987-12-09 | 1987-12-09 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01152668A true JPH01152668A (en) | 1989-06-15 |
Family
ID=18015538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31130587A Pending JPH01152668A (en) | 1987-12-09 | 1987-12-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01152668A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102007045285A1 (en) | 2007-01-29 | 2008-08-07 | Mitsubishi Electric Corp. | Semiconductor device e.g. diode, has anode electrode formed on surface of semiconductor body, where semiconductor body has protrusion that is formed at front end such that protrusion projects from inclined surface |
| JP2009049339A (en) * | 2007-08-23 | 2009-03-05 | Denso Corp | Method of manufacturing semiconductor device |
| EP2447988A1 (en) * | 2010-11-02 | 2012-05-02 | Converteam Technology Ltd | Power electronic device with edge passivation |
| WO2019116736A1 (en) * | 2017-12-12 | 2019-06-20 | 三菱電機株式会社 | Pressure-contact type semiconductor device and method for producing pressure-contact type semiconductor device |
| WO2022259503A1 (en) * | 2021-06-11 | 2022-12-15 | 三菱電機株式会社 | Pressure-contact-type semiconductor device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5010103A (en) * | 1973-05-25 | 1975-02-01 | ||
| JPS534869B2 (en) * | 1974-12-30 | 1978-02-21 | ||
| JPS6097672A (en) * | 1983-11-01 | 1985-05-31 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
-
1987
- 1987-12-09 JP JP31130587A patent/JPH01152668A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5010103A (en) * | 1973-05-25 | 1975-02-01 | ||
| JPS534869B2 (en) * | 1974-12-30 | 1978-02-21 | ||
| JPS6097672A (en) * | 1983-11-01 | 1985-05-31 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102007045285A1 (en) | 2007-01-29 | 2008-08-07 | Mitsubishi Electric Corp. | Semiconductor device e.g. diode, has anode electrode formed on surface of semiconductor body, where semiconductor body has protrusion that is formed at front end such that protrusion projects from inclined surface |
| JP2009049339A (en) * | 2007-08-23 | 2009-03-05 | Denso Corp | Method of manufacturing semiconductor device |
| EP2447988A1 (en) * | 2010-11-02 | 2012-05-02 | Converteam Technology Ltd | Power electronic device with edge passivation |
| WO2012059193A3 (en) * | 2010-11-02 | 2012-07-26 | Converteam Technology Ltd | Power electronic device with edge passivation |
| WO2019116736A1 (en) * | 2017-12-12 | 2019-06-20 | 三菱電機株式会社 | Pressure-contact type semiconductor device and method for producing pressure-contact type semiconductor device |
| WO2022259503A1 (en) * | 2021-06-11 | 2022-12-15 | 三菱電機株式会社 | Pressure-contact-type semiconductor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4904610A (en) | Wafer level process for fabricating passivated semiconductor devices | |
| KR100257429B1 (en) | Inorganic seal for encapsulation of an organic layer and method for making the same | |
| US4980019A (en) | Etch-back process for failure analysis of integrated circuits | |
| JPH01152668A (en) | Manufacture of semiconductor device | |
| US3588632A (en) | Structurally reinforced semiconductor device | |
| US20080283989A1 (en) | Wafer level package and wafer level packaging method | |
| JPS6156608B2 (en) | ||
| US5100809A (en) | Method of manufacturing semiconductor device | |
| JP2939401B2 (en) | Manufacturing method of mesa type semiconductor device | |
| JPH0864557A (en) | Manufacture of mesa type semiconductor element | |
| JPH1187572A (en) | Resin sealed semiconductor device and production thereof | |
| JPS61267333A (en) | Semiconductor device | |
| JPS62115752A (en) | Semiconductor device | |
| JPS6227548B2 (en) | ||
| JPS6097672A (en) | Semiconductor device and manufacture thereof | |
| JPS6226834A (en) | Manufacture of semiconductor device | |
| JPH01120028A (en) | Semiconductor integrated circuit | |
| JPS6112682Y2 (en) | ||
| JPH0945638A (en) | Manufacture of semiconductor device | |
| CN115084039A (en) | Guard ring structure, semiconductor structure and manufacturing method thereof | |
| JPS61294827A (en) | Manufacture of semiconductor device | |
| JPH09186179A (en) | Module for ic card | |
| JPS6037166A (en) | Manufacture of semiconductor device | |
| JP2004296770A (en) | Method for manufacturing semiconductor device | |
| JPS5998555A (en) | Manufacture of semiconductor device |