JPS6097672A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS6097672A JPS6097672A JP20652383A JP20652383A JPS6097672A JP S6097672 A JPS6097672 A JP S6097672A JP 20652383 A JP20652383 A JP 20652383A JP 20652383 A JP20652383 A JP 20652383A JP S6097672 A JPS6097672 A JP S6097672A
- Authority
- JP
- Japan
- Prior art keywords
- reinforcing plate
- metal reinforcing
- junction
- semiconductor device
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 17
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 17
- 230000002093 peripheral effect Effects 0.000 claims abstract description 11
- 238000000465 moulding Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 9
- 238000005219 brazing Methods 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 3
- 239000011247 coating layer Substances 0.000 claims description 2
- 229920002379 silicone rubber Polymers 0.000 abstract description 11
- 239000004945 silicone rubber Substances 0.000 abstract description 9
- 238000000034 method Methods 0.000 abstract description 8
- 239000004033 plastic Substances 0.000 abstract description 3
- 229920001971 elastomer Polymers 0.000 abstract 1
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 4
- 230000005684 electric field Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical group [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3185—Partial encapsulation or coating the coating covering also the sidewalls of the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、半導体装置およびその製造方法に関し、特
にその周縁部被覆方法の改良に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to an improvement in a method for covering the peripheral edge thereof.
以下、サイリスタを例にとり詳述する。 A detailed explanation will be given below using a thyristor as an example.
第１図は一般によく知られている逆阻止サイリスタの模
式図である。図において、１５は半導体基体で、該基体
１５ばその中にＰエミッタＮ１１゜Ｎベース層１２．Ｐ
ベース層１３．Ｎエミツタ層１４を有し、ＰＮ接合１９
及び２ｏが形成されている。１０は金属補強板で、半導
体基体１５の裏面全体に接着され、該基体１５の陽極を
兼ねている。また１６及び１７はそれぞれ半導体基体１
５のゲート電極及び陰極である。１８は半導体基体１５
周縁部のＰＮ接合露出部１５ａを覆う被覆材からなる被
覆層である、。FIG. 1 is a schematic diagram of a generally well-known reverse blocking thyristor. In the figure, 15 is a semiconductor substrate, and the substrate 15 has a P emitter N11°N base layer 12 . P
Base layer 13. It has an N emitter layer 14 and a PN junction 19.
and 2o are formed. A metal reinforcing plate 10 is bonded to the entire back surface of the semiconductor substrate 15 and also serves as an anode of the substrate 15. Further, 16 and 17 are the semiconductor substrate 1, respectively.
5, the gate electrode and the cathode. 18 is a semiconductor substrate 15
This is a coating layer made of a coating material that covers the exposed PN junction portion 15a at the peripheral edge.
このようなサイリスクは、以下のようにして形成される
。即ち、例えばシリコンのような半導体基体に、拡散等
の周知の方法でもってい（つかの型の異なる不純物層１
１〜１４を形成して所定の構造を得、しかる後にモリブ
デン等の金属の補強板１０をアルミニウムなどのロウ材
を介して半導体基体１５裏面に接着させ、接着後前記半
導体基体１５の周縁部を削り落とし、適当な傾斜をつけ
てメサ構造とし、その後露出したＰＮ接合部１５ａを適
当な被覆材１８、例えばシリコンゴム等により被覆する
。今述べたものはサイリスクの製造方法の一例であり、
半導体基体１５０周縁部の傾斜づけはポジティブ及びネ
ガティブベベル構造となっているが、詳述はさけるがダ
ブルポジティブ構造やその他の構造をとることもある。Such a silisk is formed as follows. That is, for example, impurity layers 1 of different types are deposited on a semiconductor substrate such as silicon by well-known methods such as diffusion.
1 to 14 to obtain a predetermined structure, and then a reinforcing plate 10 made of metal such as molybdenum is bonded to the back surface of the semiconductor substrate 15 via a brazing material such as aluminum, and after bonding, the peripheral edge of the semiconductor substrate 15 is bonded. The mesa structure is formed by cutting it off and giving an appropriate slope, and then the exposed PN junction 15a is covered with a suitable covering material 18, such as silicone rubber. What I just described is an example of the manufacturing method of Cyrisk,
The peripheral edge of the semiconductor substrate 150 has a positive and negative bevel structure, but it may also have a double positive structure or other structures, although not described in detail.
また被覆材１８はシリコンゴムの単一被覆となっている
が、ポリイミド樹脂とシリコンゴムの二重被覆となるこ
ともある。Further, the covering material 18 is a single coating of silicone rubber, but may be a double coating of polyimide resin and silicone rubber.
第２図はサイリスクエレメントの周縁部の断面模式図を
示したものである。FIG. 2 shows a schematic cross-sectional view of the peripheral edge of the silisk element.
今、サイリスクに、例えば順方向に電圧を印加すると、
第２図の斜線で示されるように、半導体基体１５中のＰ
Ｎ接合２０の両側に空乏層が形成され、これが印加電圧
を阻止することは周知のことである。このときサイリス
クエレメントの半導体基体１５の周縁のＰＮ接合露出部
１５３表面においては、第２図のように、点Ａから点Ｂ
まで空乏層が拡がり、その間で印加電圧を阻止している
。Now, if we apply a voltage to Cyrisk in the forward direction, for example,
As shown by diagonal lines in FIG.
It is well known that depletion layers are formed on both sides of N-junction 20, which blocks the applied voltage. At this time, as shown in FIG.
The depletion layer expands to the point where the applied voltage is blocked.
ところが一般的に過大な電界のかかった固体表面では沿
面放電がおこる。第２図のものにおいては、点Ａと点Ｂ
との沿面に、印加電圧による電界がかかり、当該部で沿
面放電がおこり、サイリスクは電圧阻止能力を失う。し
たがって、普通は第２図に示されたように、当該部をシ
リコンゴム１８で被覆し、ＰＮ接合露出部１５ａを安定
化させるとともに、被覆により沿面距離を点Ｃから点り
というように伸ばして電界の緩和をはかり、沿面放電を
防いでいる。However, creeping discharge generally occurs on solid surfaces where an excessive electric field is applied. In the one in Figure 2, point A and point B
An electric field due to the applied voltage is applied to the creeping surface of the capacitor, and a creeping discharge occurs in that area, causing the Cyrisk to lose its voltage blocking ability. Therefore, as shown in FIG. 2, this part is usually covered with silicone rubber 18 to stabilize the exposed PN junction part 15a and extend the creepage distance from point C to the other point. This reduces the electric field and prevents creeping discharge.
ところがサイリスクが高耐圧化してゆくにつれて印加電
圧が高まり、従来のままでは沿面電界を緩和しきれなく
なってきた。However, as the withstand voltage of Cyrisk has increased, the applied voltage has increased, and it has become impossible to alleviate the creeping electric field with the conventional method.
この発明は上記のような従来のものの問題点に鑑みてな
されたもので、ＰＮ接合露出部と金属補強板の側面の一
部または全部とにまたがって両者を被覆することにより
、沿面距離が充分とれる半導体装置およびその製造方法
を提供することを目的とじている。This invention was made in view of the problems of the conventional ones as described above, and by covering both the exposed PN junction part and part or all of the side surface of the metal reinforcing plate, a sufficient creepage distance can be achieved. The purpose of the present invention is to provide a semiconductor device that can be used for semiconductor devices and a method for manufacturing the same.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第４図および第３図は本発明の一実施例による半導体装
置およびその製造方法を示す。図において、第１．２図
と同一符号は同一のものを示し、２１は本実施例方法に
おいて使用する、被覆材成型のための型である。4 and 3 show a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention. In the figure, the same reference numerals as in FIG. 1.2 indicate the same parts, and 21 is a mold for molding the covering material used in the method of this embodiment.
以下、第３．第４図を用いて本発明の実施例を詳細に説
明する。Below, 3rd. An embodiment of the present invention will be described in detail with reference to FIG.
本実施例では従来例と同様に半導体基体１５を形成し、
これに金属補強板１０を接着し、その周縁部を切削した
後、該基体１５及び金属補強板１０を第３図に示される
ように成型用のプラスチックの型２１にはめこみ、そこ
へ硬化剤を混ぜたゲル状のシリコンゴムＡを流しこみ、
これを硬化させた後、型２１をはずして第４図に示され
るような構成としている。In this example, the semiconductor substrate 15 is formed in the same manner as in the conventional example,
After adhering the metal reinforcing plate 10 to this and cutting the peripheral edge thereof, the base body 15 and the metal reinforcing plate 10 are fitted into a plastic mold 21 for molding as shown in FIG. 3, and a hardening agent is applied thereto. Pour the mixed gel-like silicone rubber A,
After this is cured, the mold 21 is removed and the structure shown in FIG. 4 is obtained.
この構造によると、シリコンゴムの表面の沿面距離は、
Ｅ−Ｆ−Ｇ−Ｈとなり、具体的には従来例で８難であっ
たのが、本実施例では１２鶴となり、これによりサイリ
スタの耐沿面放電性が向ヒする。According to this structure, the creepage distance of the silicon rubber surface is
E-F-G-H, and specifically, the conventional example had 8 difficulties, but in this example, it became 12 troubles, thereby improving the creeping discharge resistance of the thyristor.
このように本実施例ではＰＮ接合露出部１５ａの他に陽
極電極である金属の補強板１０の側面の一部又は全部を
も覆うことにより、沿面距離を伸ばすことが可能となり
、従来のものに比較し、逆阻止サイリスクの耐沿面放電
性を大幅に向上できる。In this way, in this embodiment, by covering part or all of the side surface of the metal reinforcing plate 10, which is the anode electrode, in addition to the exposed PN junction part 15a, it is possible to extend the creepage distance, which is different from the conventional one. In comparison, the creeping discharge resistance of reverse blocking Cyrisk can be significantly improved.
なお上記実施例では被覆材の形成にプラスチックの型を
用いたが、この型はこれに限定されるものではなく、他
の方法でも本発明の目的を達成できるものであればよい
。また上記実施例では周縁部の傾斜づけ構造がポジティ
ブ及びネガティブペベル構造で、被覆が単一被覆のサイ
リスクを例にとったが、本発明はこれに限定されるもの
ではなく、ダブルポジティブベベル構造やその他の構造
のものでもよく、二重被覆のサイリスクにおいては半導
体基体とシリコンゴムとの間にポリイミド樹脂の薄膜が
存在するだけで、上記実施例と同様の効果が得られる。In the above embodiments, a plastic mold was used to form the covering material, but the mold is not limited to this, and other methods may be used as long as the objects of the present invention can be achieved. In addition, in the above embodiment, the inclined structure of the peripheral edge is a positive and negative bevel structure, and the coating is a single coating. However, the present invention is not limited to this, and the present invention is not limited to this, but a double positive bevel structure. or other structures may be used; in the case of a double-coated silice, the same effects as in the above embodiments can be obtained by simply having a thin film of polyimide resin between the semiconductor substrate and the silicone rubber.
また本発明はサイリスクだけでなく、同様な構造をもっ
た他の半導体装置、例えば、ダイオード、トランジスタ
等にも適用できることは明らかである。また上記実施例
では被覆材の形状を第４図のようにしたが、適当な型を
つくり、第５図のように被覆材にコルゲーション１８ａ
をつけることもできる。このようにすれば、沿面はＩ−
Ｊ−に−Ｌ−Ｍ−Ｎ〜Ｏとなり、さらに沿面距離が長く
することができる。Furthermore, it is clear that the present invention is applicable not only to SiRisk but also to other semiconductor devices having a similar structure, such as diodes and transistors. Further, in the above embodiment, the shape of the sheathing material was made as shown in FIG.
You can also add . If you do this, the creepage will be I-
J- becomes -L-M-N~O, and the creepage distance can be further increased.
以上のように、この発明に係る半導体装置およびその製
造方法によれば、ＰＮ接合露出部と金属補強板の側面の
一部または全部とにまたがって両者を被覆するようにし
た−ので、沿面距離を伸ばして沿面放電を防止でき、電
圧阻止能力を大幅に向上することができる効果がある。As described above, according to the semiconductor device and the manufacturing method of the same according to the present invention, the exposed PN junction portion and a part or all of the side surface of the metal reinforcing plate are coated so as to extend over the creepage distance. It is possible to prevent creeping discharge by extending the voltage, and it has the effect of greatly improving the voltage blocking ability.
第１図は従来のサイリスクの断面模式図、第２図は第１
図のサイリスクの周縁部の断面模式図、第３図は本発明
の一実施例による半導体装置の製造方法を示す図、第４
図は第３図のサイリスクの周縁部の断面模式図、第５図
は本発明の他の実施例による半導体装置の断面模式図で
ある。
１０・・・金属補強板、１１・・・Ｐエミッタ層、１２
・・・Ｎベース層、１３・・・Ｐベース層、１４・・・
Ｎエミツタ層、１５・・・半導体基体、１６・・・陰極
電極、１７・・・ゲート電極、１８・・・被覆層、１９
．２０・・・ＰＮ接合、１５ａ・・・ＰＮ接合露出部、
２１・・・成型のための型。
なお図中、同一符号は同−又は相当部分を示す。
代理人 大岩増雄
第１図
第２図
第３図
ゲル辣シリコンゴムＡ
第４図Figure 1 is a cross-sectional schematic diagram of a conventional Cyrisk, and Figure 2 is a cross-sectional diagram of a conventional Cyrisk.
FIG. 3 is a schematic cross-sectional view of the peripheral portion of the cyrisk shown in FIG.
This figure is a schematic cross-sectional view of the peripheral portion of the cyrisk in FIG. 3, and FIG. 5 is a schematic cross-sectional view of a semiconductor device according to another embodiment of the present invention. 10... Metal reinforcing plate, 11... P emitter layer, 12
...N base layer, 13...P base layer, 14...
N emitter layer, 15... Semiconductor base, 16... Cathode electrode, 17... Gate electrode, 18... Covering layer, 19
．． 20... PN junction, 15a... PN junction exposed part,
21...Mold for molding. In the drawings, the same reference numerals indicate the same or equivalent parts. Agent Masuo Oiwa Figure 1 Figure 2 Figure 3 Gel silicone rubber A Figure 4
Claims (2)
メサ型のＰＮ接合露出部が形成された半導体基体と、該
半導体基体の裏面にロウ材を介して接着された金属補強
板と、上記ＰＮ接合露出部及び上記金属補強板の側面の
一部または全部を両者にまたがって覆う被覆層とを備え
たことを特徴とする半導体装置。(1) a semiconductor substrate having at least one PN junction and a mesa-shaped PN junction exposed portion formed at the peripheral edge; a metal reinforcing plate bonded to the back surface of the semiconductor substrate via a brazing material; A semiconductor device comprising: a coating layer covering part or all of the side surface of the PN junction exposed portion and the metal reinforcing plate, spanning the both.
形成する工程と、上記半導体基体の裏面にロウ材を介し
て金属補強板を接着する工程と、上記半導体基体の周縁
部を削すメサ型のＰＮ接合露出部を形成する工程と、成
型用の型を用いて上記ＰＮ接合露出部及び上記金属補強
板の側面の一部または全部を両者にまたがって覆う被ｒ
ｉ層を形成する工程とを備えたことを特徴とする半導体
装置の製造方法。(2) forming at least one PN junction in the semiconductor substrate; bonding a metal reinforcing plate to the back surface of the semiconductor substrate via a brazing material; and cutting the periphery of the semiconductor substrate with a mesa. A step of forming an exposed PN junction part of a mold, and a step of covering the exposed PN junction part and a part or all of the side surface of the metal reinforcing plate by using a molding mold.
1. A method of manufacturing a semiconductor device, comprising the step of forming an i-layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20652383A JPS6097672A (en) | 1983-11-01 | 1983-11-01 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20652383A JPS6097672A (en) | 1983-11-01 | 1983-11-01 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6097672A true JPS6097672A (en) | 1985-05-31 |
Family
ID=16524772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20652383A Pending JPS6097672A (en) | 1983-11-01 | 1983-11-01 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6097672A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01152668A (en) * | 1987-12-09 | 1989-06-15 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
| EP0788152A2 (en) * | 1996-01-30 | 1997-08-06 | Kabushiki Kaisha Toshiba | Internal compression bonded semiconductor device with a chip frame enabling a longer creepage distance |
| JP2009049339A (en) * | 2007-08-23 | 2009-03-05 | Denso Corp | Method of manufacturing semiconductor device |
| JP2009231321A (en) * | 2008-03-19 | 2009-10-08 | Denso Corp | Silicon carbide semiconductor device and its manufacturing method |
-
1983
- 1983-11-01 JP JP20652383A patent/JPS6097672A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01152668A (en) * | 1987-12-09 | 1989-06-15 | Fuji Electric Co Ltd | Manufacture of semiconductor device |
| EP0788152A2 (en) * | 1996-01-30 | 1997-08-06 | Kabushiki Kaisha Toshiba | Internal compression bonded semiconductor device with a chip frame enabling a longer creepage distance |
| EP0788152A3 (en) * | 1996-01-30 | 1997-11-05 | Kabushiki Kaisha Toshiba | Internal compression bonded semiconductor device with a chip frame enabling a longer creepage distance |
| JP2009049339A (en) * | 2007-08-23 | 2009-03-05 | Denso Corp | Method of manufacturing semiconductor device |
| JP2009231321A (en) * | 2008-03-19 | 2009-10-08 | Denso Corp | Silicon carbide semiconductor device and its manufacturing method |
| JP4535151B2 (en) * | 2008-03-19 | 2010-09-01 | 株式会社デンソー | Method for manufacturing silicon carbide semiconductor device |
| US7825017B2 (en) | 2008-03-19 | 2010-11-02 | Denso Corporation | Method of making silicon carbide semiconductor device having multi-layered passivation film with uneven surfaces |
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