JPH0115241Y2 - - Google Patents
Info
- Publication number
- JPH0115241Y2 JPH0115241Y2 JP1981040032U JP4003281U JPH0115241Y2 JP H0115241 Y2 JPH0115241 Y2 JP H0115241Y2 JP 1981040032 U JP1981040032 U JP 1981040032U JP 4003281 U JP4003281 U JP 4003281U JP H0115241 Y2 JPH0115241 Y2 JP H0115241Y2
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- resistance value
- series
- addition
- resistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000006243 chemical reaction Methods 0.000 claims description 10
- 230000000295 complement effect Effects 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- -1 Since gate voltage Substances 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Description
【考案の詳細な説明】
本考案は抵抗ラダー型Ｄ／Ａ変換回路に関す
る。[Detailed Description of the Invention] The present invention relates to a resistance ladder type D/A conversion circuit.
抵抗ラダー型Ｄ／Ａ変換回路は回路構成が簡単
でスタテイツク動作であるため応答が速く、雑音
発生も少い等の利点の為に広く用いられている。 Resistance ladder type D/A conversion circuits are widely used because of their advantages such as simple circuit configuration, static operation, fast response, and low noise generation.
MOS型FET（以下MOSTと略す）を用いた集
積回路中に形成する抵抗ラダー型Ｄ／Ａ変換回路
の代表例を第１図に示す。同図に於て、T1，T2，
T3，T4は夫々相補関係にあるデイジタル入力信
号Ａ，，Ｂ，が夫々ゲートに印加される
MOST対で、各MOST（T1，T2）、（T3，T4）に
対して直列に直列抵抗RS1，RS2が接続されてい
る。RM1，RM2はこのMOST（T1，T2）、（T3，
T4）と直列抵抗RS1，RS2とに対して並列に接続
された終端補正の為の補正抵抗であつて、これ等
のMOST対（T1，T2）、（T3，T4）と、直列抵抗
RS1，RS2と、補正抵抗RM1，RM2と、で１ビツ
トのＤ／Ａ変換器DA1，DA2が構成されており、
これ等の各Ｄ／Ａ変換器DA1，DA2はアナログ量
加算の為の加算抵抗RAを介して連結されてい
る。尚、Ｅは基板（アース）電位、Ｖは電源ライ
ンを夫々示している。 FIG. 1 shows a typical example of a resistance ladder type D/A conversion circuit formed in an integrated circuit using MOS type FETs (hereinafter abbreviated as MOST). In the same figure, T 1 , T 2 ,
At T 3 and T 4 , complementary digital input signals A, B are applied to the gates, respectively.
In the MOST pair, series resistors RS 1 and RS 2 are connected in series to each MOST (T 1 , T 2 ), (T 3 , T 4 ). RM 1 and RM 2 are this MOST (T 1 , T 2 ), (T 3 ,
T 4 ) and series resistors RS 1 , RS 2 are connected in parallel for termination correction, and these MOST pairs (T 1 , T 2 ), (T 3 , T 4 ) and series resistance
RS 1 , RS 2 and correction resistors RM 1 , RM 2 constitute 1-bit D/A converters DA 1 , DA 2 ,
These D/A converters DA 1 and DA 2 are connected via an addition resistor RA for addition of analog quantities. Note that E indicates a substrate (earth) potential, and V indicates a power supply line.
斯る構成のＤ／Ａ変換回路に於て、出力電圧は
ラダーを構成する各抵抗の比に依つて決まるので
あるから、もし各抵抗値のON抵抗値が十分小さ
ければ、一般に各抵抗の温度係数は集積回路内で
は良く揃つているので、温度ドリフトの小さい
Ｄ／Ａ変換回路が実現される。 In a D/A converter circuit with such a configuration, the output voltage is determined by the ratio of each resistor that makes up the ladder, so if the ON resistance value of each resistor value is sufficiently small, the temperature of each resistor generally increases. Since the coefficients are well aligned within the integrated circuit, a D/A conversion circuit with small temperature drift can be realized.
然し乍らON抵抗の小さいMOSTはその面積が
大きなものとなり、集積回路化には不向きであ
り、またMOSTのON抵抗の温度依存性はかなり
大きいので、第１図に示した現存のＤ／Ａ変換回
路ではアナログ出力の温度ドリフトを抑える事は
難かしい。 However, a MOST with a small ON resistance requires a large area, making it unsuitable for integration into an integrated circuit, and the temperature dependence of the ON resistance of the MOST is quite large, so the existing D/A converter circuit shown in Figure 1 Therefore, it is difficult to suppress the temperature drift of analog output.
本考案は斯様な問題点に鑑みて為されたもので
あつて、アナログ出力のドリフトを軽減する事を
目的としている。 The present invention was devised in view of such problems, and its purpose is to reduce the drift of analog output.
第２図は本考案Ｄ／Ａ変換回路を示しており、
T1，T2，T3，T4は夫々MOST対、RS1，RS2は
直列抵抗、RM1，RM2は補正抵抗、RAは加算抵
抗で、夫々第１図と同じである。本考案の異ると
ころは各補正抵抗RM1，RM2に直列に補正
MOST（TM1，TM2）を挿入すると共に、加算
抵抗RAに直列に加算MOST（TA）を挿入したと
ころにある。ここでMOST（T1，T2，T3，T4）、
補正MOST（TM1），（TM2）、加算MOST（IA）
のON抵抗値および直列抵抗RS1，RS2、補正抵
抗RM1，RM2、加算抵抗値RAの抵抗値を、夫々
rT1，rT2，rT3，rT4，rTM1，rTM2，rTA，rRS1，rRS2，
rRM1，rRM2，rRAとする。 Figure 2 shows the D/A conversion circuit of the present invention.
T 1 , T 2 , T 3 , and T 4 are MOST pairs, RS 1 and RS 2 are series resistors, RM 1 and RM 2 are correction resistors, and RA is an addition resistor, which are the same as in FIG. 1, respectively. The difference in this invention is that correction is performed in series with each correction resistor RM 1 and RM 2 .
This is where the MOST (TM 1 , TM 2 ) are inserted and the addition MOST (TA) is inserted in series with the addition resistor RA. Here, MOST(T 1 , T 2 , T 3 , T 4 ),
Correction MOST (TM 1 ), (TM 2 ), addition MOST (IA)
The ON resistance value and the resistance value of series resistance RS 1 , RS 2 , correction resistance RM 1 , RM 2 , and addition resistance value RA are respectively
r T1 , r T2 , r T3 , r T4 , r TM1 , r TM2 , r TA , r RS1 , r RS2 ,
Let r RM1 , r RM2 , r RA .
そして加算抵抗（RA）と前記加算MOST
（TA）のON抵抗との合成抵抗値（（rRA＋rTA）に
占める加算MOST（TA）のON抵抗値の割合、前
記補正抵抗RM1，RM2と前記補正MOST（TM1，
TM2）のON抵抗との合成抵抗値（rRM1＋rTM1），
（rRM2＋rTM2）に占める補正MOSTのON抵抗値の
割合、前記直列抵抗（RS1），（RS2）とこの直列
抵抗に直列接続されたMOST対（T1，T2）、
（T3，T4）の一方または他方のON抵抗との合成
抵抗値（rRS1＋rT1），（rRS1＋rT2），（rRS2＋rT3）
，
（rRS2＋rT4）に占めるMOST対の一方または他方
のON抵抗値の割合を、一定に設定している。つ
まり、
rTA／（rRA＋rTA）＝rTM1／（rRM1＋rTM1）＝rTM2／
（rRM2＋rTM2）
rTA／（rRA＋rTA）＝rTM1／（rRM1＋rTM1）＝rTM2／
（rRM2＋rTM2）
＝rT1（rRS1＋rT1）＝rT2／（rRS1＋rT2
）＝rT3／（rRS2＋rT3）＝rT4／（rRS2＋rT4）
となるように、MOST（TM1），（TM2），（TA）
の寸法やゲート電圧が設定される。 and the addition resistor (RA) and the addition MOST
The ratio of the ON resistance value of addition MOST (TA) to the combined resistance value ((r RA + r TA ) with the ON resistance of (TA), the correction resistances RM 1 , RM 2 and the correction MOST (TM 1 ,
Combined resistance value (r RM1 + r TM1 ) with ON resistance of TM 2 ),
The ratio of the ON resistance value of the corrected MOST to (r RM2 + r TM2 ), the series resistance (RS 1 ), (RS 2 ) and the MOST pair (T 1 , T 2 ) connected in series to this series resistance,
Combined resistance value (r RS1 + r T1 ), (r RS1 + r T2 ), (r RS2 + r T3 ) with one or the other ON resistance of ( T 3 , T 4 )
，
The ratio of the ON resistance value of one or the other of the MOST pair to (r RS2 + r T4 ) is set to be constant. In other words, r TA / (r RA + r TA ) = r TM1 / (r RM1 + r TM1 ) = r TM2 /
(r RM2 + r TM2 ) r TA / (r RA + r TA ) = r TM1 / (r RM1 + r TM1 ) = r TM2 /
(r RM2 + r TM2 ) = r T1 (r RS1 + r T1 ) = r T2 / (r RS1 + r T2
) = r T3 / (r RS2 + r T3 ) = r T4 / (r RS2 + r T4 ), MOST (TM 1 ), (TM 2 ), (TA)
The dimensions and gate voltage are set.
斯る回路構成に於て温度変化が生じた場合、各
抵抗の抵抗値とMOSTのON抵抗値とは夫々温度
係数が異る為、抵抗要素中に占めるMOSTのON
抵抗値の割合は変化する。しかしこの変化は各抵
抗要素について一斉に生じるので、各合成抵抗同
士の比率が変化しない事は明らかである。各
MOST（T1），（T2），（T3），（T4）、補正MOST
（TM1），（TM2）、加算MOST（TA）とこの
MOSTと夫々対応する抵抗（RS1），（RS2），
（RM1），（RM2），（RA）との合成抵抗値に占め
るMOSTのON抵抗値の割合を一定にすると云う
条件が満足されれば、MOSTのON抵抗値が或る
程度の大きさであつても温度ドリフトの小さな
Ｄ／Ａ変換回路が実現される。 If a temperature change occurs in such a circuit configuration, the resistance value of each resistor and the ON resistance value of MOST have different temperature coefficients, so the ON resistance of MOST that occupies the resistance element will change.
The percentage of resistance changes. However, since this change occurs for each resistance element all at once, it is clear that the ratio of each combined resistance does not change. each
MOST (T 1 ), (T 2 ), (T 3 ), (T 4 ), corrected MOST
(TM 1 ), (TM 2 ), addition MOST (TA) and this
Resistors (RS 1 ), (RS 2 ), corresponding to MOST, respectively
If the condition that the ratio of the MOST ON resistance value to the combined resistance value of (RM 1 ), (RM 2 ), and (RA) is constant is satisfied, the MOST ON resistance value will be large to a certain extent. A D/A conversion circuit with small temperature drift can be realized even when the temperature is low.
扨て本考案回路に於て、MOST（T1），（T2），
（T3），（T4），（TM1），TM2）はソース或いはド
レインの何れかがアース電位Ｅ又は電源ラインＶ
の固定電位にあるので、三極管領域での動作であ
れば、ソースに対して有効なゲート電圧及び基板
バイアス効果等は略一定であり、ON抵孔の制御
は容易である。 Therefore, in the circuit of the present invention, MOST (T 1 ), (T 2 ),
(T 3 ), (T 4 ), (TM 1 ), TM 2 ) have either the source or drain connected to the ground potential E or the power line V.
Since the voltage is at a fixed potential, the gate voltage and substrate bias effect effective for the source are approximately constant when operating in the triode region, and the ON resistance can be easily controlled.
一方加算MOST（TA）に就いてはデイジタル
入力信号に応じてソース、ドレイン電圧は絶えず
変化し、その為にこの加算MOST（TA）のゲー
ト電圧を基板に対して一定に保つたとしてもソー
スに対するゲート電圧並びに基板バイアス効果等
は絶えず変動するので、該MOST（TA）のON抵
抗値の制御は困難である。このような点から加算
MOST（TA）のゲート電圧を該MOST（TA）の
ソース、ドレイン電圧の変動範囲よりも十分大き
くとり、かつこのMOST（TA）としてデプレツ
シヨン型MOSTを用いて実効的ゲート電圧を極
力大きくすることに依り、そのソース、ドレイン
電圧の変動に依る実効的ゲート電圧の変動を相対
的に小さくする事が出来る。 On the other hand, regarding the addition MOST (TA), the source and drain voltages constantly change depending on the digital input signal, so even if the gate voltage of this addition MOST (TA) is kept constant with respect to the substrate, Since gate voltage, substrate bias effects, etc. constantly vary, it is difficult to control the ON resistance value of the MOST (TA). Addition from such points
The gate voltage of the MOST (TA) is set to be sufficiently larger than the fluctuation range of the source and drain voltages of the MOST (TA), and a depletion type MOST is used as the MOST (TA) to increase the effective gate voltage as much as possible. Therefore, fluctuations in the effective gate voltage due to fluctuations in the source and drain voltages can be made relatively small.
本考案は以上の説明から明らかな如く、補正抵
抗と加算抵抗とに夫々直列にMOSTを接続し、
この各抵抗値rRA，rRS1，rRS2，rRM1，rRM2とこの抵
抗と対応するMOSTのON抵抗値rTA，rT1または
rT2，rT3またはrT4，rTM1，rTM2との合成抵抗値に占
めるMOSTのON抵抗値の割合を一定に設定して
いるので、各MOSTのON抵抗の温度依存性に由
来するアナログ出力のドリフトを軽減する事が出
来る。 As is clear from the above explanation, the present invention connects the MOST in series with the correction resistor and the addition resistor, respectively.
These resistance values r RA , r RS1 , r RS2 , r RM1 , r RM2 and the corresponding MOST ON resistance values r TA , r T1 or
Since the ratio of the MOST ON resistance value to the combined resistance value of r T2 , r T3 or r T4 , r TM1 , r TM2 is set to a constant value, the analog value derived from the temperature dependence of the ON resistance of each MOST is Output drift can be reduced.
第１図は現存するＤ／Ａ変換回路の回路図、第
２図は本考案Ｄ／Ａ変換回路の回路図であつて、
ＴはMOST、RSは直列抵抗、RMは補正抵抗、
RAは加算抵抗、を夫々示している。
Figure 1 is a circuit diagram of an existing D/A conversion circuit, and Figure 2 is a circuit diagram of the D/A conversion circuit of the present invention, where T is MOST, RS is a series resistor, RM is a correction resistor,
RA indicates the additive resistance.
Claims (1)
るMOST対と、該MOST対に直列に接続された
直列抵抗と、このMOST対と直列抵抗とに対し
て並列に接続された終端補正の為の補正抵抗と、
から成るＤ／Ａ変換器をアナログ量の加算の為の
加算抵抗を介して連結した抵抗ラダー型Ｄ／Ａ変
換回路に於て、 上記補正抵抗と加算抵抗に夫々直列に補正
MOSTと加算MOSTを接続すると共に、 前記加算抵抗と前記加算MOSTのON抵抗との
合成抵抗値に占める加算MOSTのON抵抗値の割
合、 前記補正抵抗と前記補正MOSTのON抵抗との
合成抵抗値に占める補正MOSTのON抵抗値の割
合、 前記直列抵抗とこの直列抵抗に直列接続された
MOST対の一方または他方のON抵抗との合成抵
抗値に占めるMOST対の一方または他方のON抵
抗値の割合、 が等しくなるようにMOSTのON抵抗値を設定
した事を特徴とする抵抗ラダー型Ｄ／Ａ変換回
路。[Claims for Utility Model Registration] A pair of MOSTs into which mutually complementary digital signals are input, a series resistor connected in series to the pair of MOSTs, and a pair of resistors connected in parallel to the pair of MOSTs and the series resistor. a correction resistor for correcting the termination,
In a resistance ladder type D/A conversion circuit in which a D/A converter consisting of a
In addition to connecting the MOST and the addition MOST, the ratio of the ON resistance value of the addition MOST to the combined resistance value of the addition resistance and the ON resistance of the addition MOST, the combined resistance value of the correction resistance and the ON resistance of the correction MOST The ratio of the ON resistance value of the corrected MOST to the above series resistance and that connected in series to this series resistance
A resistor ladder type characterized in that the ON resistance value of the MOST is set so that the ratio of the ON resistance value of one side or the other side of the MOST pair to the combined resistance value of the ON resistance value of one side or the other side of the MOST pair is equal. D/A conversion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981040032U JPH0115241Y2 (en) | 1981-03-20 | 1981-03-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1981040032U JPH0115241Y2 (en) | 1981-03-20 | 1981-03-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57152840U JPS57152840U (en) | 1982-09-25 |
| JPH0115241Y2 true JPH0115241Y2 (en) | 1989-05-08 |
Family
ID=29837144
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1981040032U Expired JPH0115241Y2 (en) | 1981-03-20 | 1981-03-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0115241Y2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5535596A (en) * | 1978-09-01 | 1980-03-12 | Siemens Ag | Da converter |
| JPS55156422A (en) * | 1979-05-25 | 1980-12-05 | Nec Corp | Digital-analog converter |
-
1981
- 1981-03-20 JP JP1981040032U patent/JPH0115241Y2/ja not_active Expired
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5535596A (en) * | 1978-09-01 | 1980-03-12 | Siemens Ag | Da converter |
| JPS55156422A (en) * | 1979-05-25 | 1980-12-05 | Nec Corp | Digital-analog converter |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57152840U (en) | 1982-09-25 |
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