JPH01141412A - Pwm converting circuit - Google Patents

Abstract

PURPOSE:To cause a ripple, after a PWM output signal passes an integrating circuit, to be small with the small quantity of hardwares by reading two patterns from a pattern storing means according to digital data to which a pulse width modulation(PWM) conversion is executed, synthesizing them, and outputting an optimum PWM output pattern. CONSTITUTION:A PWM signal, in which a first pattern is repeated 2N times in a prescribed time period and, simultaneously, a second pattern is inserted into the part of the 2N-1 delimitation of the first pattern, is outputted. In such a case, the first and second patterns '010010010010010' and '101110111011101' are the patterns in which the data of '1' are uniformly arranged by a number indicated by the high order N bit and low order N bit of input data. Consequently, the number of pulses contained in the PWM signal and a pulse period are both dynamically changed according to the input data. Namely, the pulse period is made short. For such a reason, the ripple, after the PWM output signal passes the integrating circuit, can be made small.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention applies pulse width modulation (Pulse Width Modulation) to digital data.
The present invention relates to a PWM conversion circuit that performs Width Modulation (PWM), and particularly relates to a PWM conversion circuit that generates and outputs a PWM signal in which the sum of pulse widths of pulses repeatedly output during a fixed period is a value proportional to digital data.

[Prior art] Digital data is input and a plurality of pulse signals are output within a predetermined time period, and the sum of the pulse widths of the pulse signals in the time period is set to a length proportional to the value of the digital data. The PWM conversion circuit is used, for example, at a stage before an integrator in D/A conversion. This type of PWM conversion circuit is required to have a small size and a simple configuration as various consumer devices become digitalized.

FIG. 5 is a blower diagram showing a conventional PWM conversion circuit. For example, 8-bit digital data DATA is
8-bit data latch circuit 4 based on latch signal
It is held at 1. Of the 8-bit digital data DATA held in this data latch circuit 41, the upper 5 bits of data DH are given as one input of the 5-bit first comparator 42, and the lower 3 bits of data DL are
It is given as one input of the bit second comparator 43.

On the other hand, the 5-bit first counter 44 counts the clock signal CKO and converts the count value CN1 into the first counter 44.
is applied to the other input of the comparator 42. The match signal M from the first comparator 42 is: D type flip-flop 45
is applied to reset the output of the flip-flop 45. Further, the overflow signal F of the counter 44 is also given to the D-type flip-flop 45.
Set the output of . On the other hand, the content of the counter 44 is “3”.
The clock pulse CKI output just before it becomes 1” is
A 3-bit second counter 46 is provided. This second counter 46 counts the clock pulse CK1 each time the first counter 44 makes one round, and supplies the count value CN2 to the other input of the second comparator 43. Then, the output PH(
main pulse) and the output PL of the second comparator 43 (sub pulse)
The OR circuit 47 outputs the value obtained by logically adding the values and the values as a PWM signal.

Now, if the period of the clock signal CKO is T, then this circuit has a time period of 32T defined by 28T=2567.
The value of the upper 5 bits of data DH of the 8-bit digital data DATA × the value of the data DH of the upper 5 bits of the 8-bit digital data DATA
The main pulses PH with a width of T are output, and these eight main pulses PH have a width T of the number indicated by the lower 3 bits of data DL.
The sub-pulses PL are added one pulse at a time to the main pulse PH.

FIG. 6 shows the waveforms of the main pulse PH and the sub-pulse PL when the digital data DATA is “PaA3H”. That is, in this case, the upper 5 bits of DATA are “1”.
0100” = “20”, lower 3 bits are “011”
= "3", so the pulse width of the main pulse PH is 207 and the number of additional sub pulses PL is 3°° as shown in the figure.
Total pulse width in period 256T is 21X3+20X5
=163=A3H.

This circuit has the advantage that a PWM conversion circuit can be easily constructed using a counter, a comparator, and the like.

[Problems to be Solved by the Invention] In the conventional PWM conversion circuit described above, the main pulse PH is determined by comparing the upper m bits (man) of the n bits of digital data to be PWM converted with the count value of the counter. Determine the pulse width. In addition, in this PWM conversion circuit, the number of main pulses PH during period 2''XT (T is the clock period) is 2''-'1, and the period of main pulse PH is 2''.
1×T, and these are predetermined by the hardware configuration of the PWM circuit, regardless of the value of digital data to be PWM converted.

On the other hand, the pulse signal after PWM conversion generally passes through an integrating circuit and is converted into an analog signal, but in conventional PWM conversion circuits, the period and number of main pulses are fixed as described above, and furthermore, due to the structure, the main pulse Extremely shorten the period of
Since it is not possible to increase the number of main pulses, there is a problem that a relatively large ripple component is included in the analog signal that has passed through the integrating circuit.

The present invention has been made in view of such problems, and an object of the present invention is to provide a PWM conversion circuit that can obtain a PWM signal with less ripple components when converted to analog and has a simple configuration.

[Means for Solving the Problems] The PWM conversion circuit according to the present invention includes a data holding means for holding 2N bits of input data to be processed, and a data holding means for holding 2N bits of input data to be processed, and an upper part of the 2N bits of input data held in the data holding means. N
selection means for sequentially selecting the bit and the lower N bits;
The data of the upper N bits and the data of the lower N bits selected by this selection means are sequentially input as addresses, and the first . a pattern storage means for sequentially outputting a second pattern; a first shift register for holding the first pattern and outputting it cyclically; a second shift register that shifts and outputs the second pattern each time the first . and an OR means for ORing the output from the second shift register and outputting it as a PWM signal.

And the above-mentioned 1. The second pattern is "1" as many as the number indicated by the N-bit address given to the pattern storage means.
This pattern includes data of 1, and is characterized in that these "1" data are approximately evenly distributed from the upper bit to the lower bit.

[Operation] According to the present invention, within a predetermined time period, the first
A PWM signal is output in which the pattern is repeated 2N times and the second pattern is interpolated into 2N-1 divisions of the first pattern. Here, the first. In the second pattern, the number of "1" data indicated by the upper N bits and lower N bits of the input data is evenly distributed, so the number of pulses and the pulse period included in the above PWM signal are Both change dynamically depending on input data. In other words, the number of pulses is greater than before,
The pulse period changes to become shorter than before. Therefore, the ripple of the PWM output signal obtained by the present invention after passing through the integrating circuit can be made extremely small.

In addition, originally, for 2N bits of input data, the number of patterns that should be prepared in order to obtain pulse signals with the corresponding number and period is 22N, but in the present invention, the input data is divided into upper N bits and lower N bits. A pattern for the 2N-bit input data is generated by combining a first pattern obtained by the upper N bits and a second pattern obtained by the lower N bits. Since the first pattern and the second pattern are the same, in the present invention, the number of patterns to be prepared or generated is
2N pieces is enough. Therefore, according to the present invention, the configuration is simplified.

[Example] Hereinafter, an example of the present invention will be described based on the accompanying drawings.

FIG. 1 is a block diagram showing a PWM conversion circuit according to a first embodiment of the present invention.

8-bit digital data DATA that is input data
A latch signal that provides latch timing for this digital data DATA is input to an 8-bit data latch circuit 11. The frequency of the latch signal is 1/3
The frequency is 2 MHz and the pulse width is 2 μsec. Digital data DATA held in the data latch circuit 11
Of these, the upper 4 bits of data DH and the lower 4 bits of data DL are introduced into each input terminal of the multiplexer 12, respectively.

On the other hand, the latch signal is given to the first delay circuit 13. The first delay circuit 13 delays the latch signal by 5 μsec and outputs the delayed signal LDI. This delay signal LDI is further transmitted to the second delay circuit 14.
has been entered. The second delay circuit 14 further delays the delay signal LDI by 5 μsec to generate a delay signal LS2.
Output.

These delayed signals LDI and LD2 are input to D-type flip-flops (D-FF) 15, respectively.

The D-type flip-flop 15 has a delay signal LD1 of “1”.
When the output becomes “1”, the delay signal LD2 becomes “1”.
”, the output is set to “0” and the output is output to the multiplexer 12 as the selection signal SEL.

The multiplexer 12 selects the upper 4 bits of data D of the digital data DATA sequentially selected by the selection signal SEL.
H and the lower 4 bits of data DL are stored in a ROM (Read
0nly Memory> Give as 16 addresses AD. The ROM 16 is a pattern storage means that stores patterns as shown in FIG.

This pattern is a 15-bit pattern that includes a number of "1"s corresponding to the value of the address, and is a pattern in which "1" data is evenly distributed from the upper bit to the lower bit. This ROM 16 receives a pattern C of a designated address according to a read signal RD obtained by ORing the delay signals LDI and LD2 by an OR circuit 17.
Outputs 0NT. C0NT output from ROM16
is input to the upper bit side of the 16-bit first data latch circuit 18 and second data latch circuit 19.

"0" is always applied to the LSB of these data latch circuits 18 and 19, and the delay signals LDI and LD2 are applied to the latch signals, respectively. The data stored in the first data latch circuit 18 is input to the cyclic first shift register 20, and the data is input to the second data latch circuit 1.
The data stored in 9 is input to the second shift register 21.

On the other hand, the 8 MHz clock signal CKO is given as a shift clock signal to the first shift register 20 and is also input to the frequency divider circuit 22.
divides the clock signal CKO by 16 and obtains 0.5)41(z
outputs the clock signal CKI. This clock signal C
KI is given as a shift clock signal to the second shift register 21 and is also input to the frequency dividing circuit 23 . The frequency dividing circuit 23 further divides the clock signal CKI by 16 and outputs a 1/32 MHz clock signal CK2.

This clock signal CK2 is applied to two shift registers 20
．． 21 as a latch signal.

The shift registers 20 and 21 parallel-serial convert the stored data based on the clock signals CKO and CKI, and
pulse PH and second pulse PL, respectively. These pulses PH and PL are logically summed by an OR circuit 24 and output as a PWM signal.

Next, the operation of this embodiment configured as described above will be explained.

A calculation unit (not shown) outputs calculation results (digital data DATA) at a cycle of 31.25 μsec. Since the frequency of the latch signal is 1/3214)1z and the period is 31.25 μSeC, each time data DATA is sent out, the data latch circuit 11 sends the data D
ATA is latched. When the delay signal LDI becomes "1'" 5 μsec after the latch signal becomes "1n," the D-type flip-flop 15 is set and the selection signal SEL becomes "1". The content DH of the upper 4 bits of the stored data is output as the address AD of the ROM 16.

The ROM 16 outputs a 15-bit first pattern based on the address AD specified by the upper 4 bits of data in the data latch circuit 11 in synchronization with the read signal RD. At this time, the data latch circuit 18 is given the delay signal LDI as a latch signal, so the first pattern is input to the data latch circuit 18.

Next, when the delay signal LD2 becomes "1" with a further delay of 5 μsec from the delay signal LDI, the D-type flip-flop 15
is reset, the selection signal SEL becomes "O", and the content DL of the lower 4 bits of the data stored in the data latch circuit 11 is output by the multiplexer 12 as the address AD of the ROM 16. The ROM 16 stores the lower 4 data of the data latch circuit 11 in synchronization with the read signal RD.
A 15-bit second pattern is output based on the address AD specified by the bit. At this time, since the delay signal LD2 is given to the data latch circuit 19 as a latch signal, the second pattern is the same as that of the data latch circuit 1.
9 Heratsuchi is received.

For example, data D latched in the data latch circuit 11
Assuming that ATA is "5BM", a pattern (first pattern) of "010010010010010" is inputted to the data latch circuit 18 with a delay of 5 μsec from the latch signal, and "10111" is inputted to the data latch circuit 19.
0111011101” pattern (second pattern)
is input 10 μsec later than the latch signal. After the data is latched into the data latch circuit 11 in this way,
1st during 1゛0μSeC. The second patterns are latched into data latch circuits 18 and 19, respectively.

In the data latch circuits 18 and 19, “°” is applied to the LSB, respectively.
16-bit pattern with 0'' added “0010010
010010010”, “0101110111011
101' is retained. These patterns are 1/32M
At the rising edge of the Hz clock signal CK2, the signals are input to the shift registers 20 and 21, respectively, and are immediately shifted. The data input to the shift register 20 is cyclically right-shifted at 8 MHz based on the clock signal CKO, and the data input to the shift register 21 is right-shifted at 0.5 MHz based on the clock signal CKI.

FIGS. 3(a) and 3(b) show the first . FIG. 3 is a timing chart diagram showing second pulses PH and PL. If the period of the clock signal CKO is T, the first pulse PH"01001001 is generated during 16T.
00100100" is serially output, and each bit of the second pulse PL is output at the LSB output timing with "0" inserted.

Therefore, PW obtained by ORing these pulses PH and PL
The M output signal has a pattern in which the first pulse PH is repeated 16 times and the second pulse PL is interpolated bit by bit at the output timing of the LSB of the first pattern PH.

That is, the OR circuit 24 performs 5X 16+ 11=91 during 31.25 μsec from the rise of the clock signal CK2.
='“58M” “1” and 165 (256-91=
165) and outputs a PWM pulse consisting of "0".

Similarly, if the data latched by the data latch circuit 11 is, for example, "B A H", pulses PH and PL as shown in FIG. 3(b) are sent to each shift register 20.
It is output from 21.

As is clear from these, according to the circuit of this example,
The pulse period T' of the obtained PWM pulse changes dynamically depending on the content of the data.

Since these have a shorter period and a greater number of pulses than those obtained by conventional circuits, the ripples of the analog signal obtained when these are integrated are also small.

Also, the number of patterns that should be prepared for 8-bit data is 28=256, but according to this circuit,
Since the 8-bit data is divided into upper and lower 4 bits and the two patterns defined by these are combined to obtain the desired pattern, only 2' = 16 patterns are required. , ROM 16 can also have a simple configuration.

In the above embodiment, the 4-bit address ROM 16 is used as the pattern storage circuit, but if the pattern storage circuit is configured as shown in FIG. 4, the number of patterns to be stored can be further reduced.

In FIG. 4, of the 4-bit address AD, the lower 3 bits are input to the first inverter circuit 31. This inverter circuit 31 inverts the lower three bits of address AD only when the MSB of address AD is "1". The output of the inverter circuit 31 is a 3-bit address R
It is given to OM32 as address information. ROM
32 is the address “0000” of the pattern in FIG.
” to “0111” are stored.The output of the ROM 32 is further input to the second inverter circuit 33.The inverter circuit 33 is injected only when the MSB of the address AD is “1”. The bits of the pattern read from the ROM 16 are inverted and the data latches 18.
Output to 19.

This circuit has addresses “0000” to “0000” in FIG.
The pattern up to “0111” is “1111” to “100”
The number of stored patterns is reduced to 1/2 of that in FIG. 2 by taking advantage of the fact that the bits are exactly reversed from the pattern up to 0''.

Note that the present invention is not limited to the embodiments described above. For example, the bus width of the bus, the capacity of the ROM, the frequency latch of the clock signal, the bit width of the shift register, etc. can be changed as appropriate. Similarly, the data pattern stored in the ROM can also be set arbitrarily.

[Effects of the Invention] As explained above, the PWM conversion circuit of the present invention uses a pattern storage means, reads two patterns from the pattern storage means according to the value of digital data to be PWM converted, and converts the two patterns. Optimal PWM by combining
By outputting the output pattern, the period and number of pulses of the PWM output signal can be dynamically changed according to the value of the digital data to be PWM converted with a small amount of hardware, and the pulse period and number of pulses of the PWM output signal can be changed after passing through the integration circuit. Ripple can be made extremely small.

[Brief explanation of the drawing]

FIG. 1 is an operation timing chart of a PWM conversion circuit according to a first embodiment of the present invention, and FIG. 4 is a block diagram showing a pattern storage means in a PWM conversion circuit according to a second embodiment of the present invention. , FIG. 5 is a block diagram of a conventional PWM conversion circuit, and FIG. 6 is an operation timing diagram of the circuit. 11.18.19, 41; Data latch circuit, 12; Multiplexer, 13, 14; Delay circuit, 15, 45
．． D-type flip-flop, 16°32; ROM, 1
7.24,47. OR circuit, 20.21; Shift register, 22.23; Frequency divider circuit, 31, 33; Inverter circuit, 42.43; Comparator, 44.46, Counter

Claims (3)

[Claims] (1) data holding means for holding 2N bits of input data; selection means for sequentially selecting the upper N bits and lower N bits of the input data held in the data holding means; Each of the above N bits of data is sequentially input as an address, and a 2^N-1 bit pattern is created in which the number of "1" data corresponding to the value of this address is distributed approximately evenly from the upper bit to the lower bit. a pattern storage means for outputting each, and holding a first pattern outputted from the pattern storage means by specifying an address of the upper N bits, and circulating the first pattern based on a predetermined clock signal; a first shift register for shifting and outputting the first pattern; and holding a second pattern output from the pattern storage means by specifying an address of the lower N bits;
Each time the first shift register circulates once, the second shift register
a second shift register that shifts and outputs a pattern of
A PWM conversion circuit comprising an OR means for ORing the shift outputs from the first and second shift registers and outputting the resulting value as a PWM signal. (2) The pattern storage means stores a 2^N-1 bit pattern in which a number of "1" data corresponding to the value of the N-bit address is distributed approximately evenly from the upper bit to the lower bit. The PWM conversion circuit according to claim 1, which is a ROM. (3) the pattern storage means includes a first inverter circuit that inverts and outputs the lower N-1 bits of the N-bit address only when the value of the most significant bit of the address is "1"; The N-1 bit data from this inverter circuit is used as an address, and the number of "1" data corresponding to the value of the address is distributed approximately equally from the upper bit to the lower bit. R memorized the pattern
It is characterized by comprising an OM and a second inverter circuit that inverts and outputs the output of the ROM only when the value of the most significant bit of the N-bit address is "1". PWM according to claim 1
conversion circuit.