SU1529451A1 - Protection-rate scaler with fractional divison ratio - Google Patents

Abstract

The invention relates to a pulse technique and can be used in automation and computing devices and in frequency synthesizers. The purpose of the invention is to expand the range of variation of the division ratio by providing the possibility of dividing by a factor less than one while simplifying the device — achieved by introducing counters 10, 11 pulses into the frequency divider, memory register 12 and creating new functional connections. In addition, the frequency divider contains 1 pulse generator, registers 2, 3 memory, adders 4, 5, frequency divider 6, comparison block 7, pulse counter 8, buses 9, 13, 14, 15 output, input, resolution, coefficient setting division, respectively. 1 hp f-ly, 2 ill.

Description

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The invention relates to a pulse technique and can be used in automation and computing devices and in frequency synthesizers.

The purpose of the invention is to expand the range of variation of the division ratio by allowing division by a factor less than one while simplifying the device.

The figure shows the structural scheme of the divider; Fig 2 - structural diagram of the first adder

A pulse frequency divider with a fractional division factor comprises a pulse generator 1, first 2 and second 3 memory registers, first 4 and second 5 adders, frequency divider 6, comparison unit 7, first 8-pulse counter and output bus 9, The information output of the second memory register 3 is connected to the first input of the first adder 4, the second input and output of the comparison unit 7 are connected respectively to the information output and the zero input input of the first pulse counter 8, the second 10 and the third 11 pulse counters, the third re memory 12, input bus 13, resolution bus 14 and bus 15 for specifying the division factor, the input bus 13 connected to the generator start input

1 pulses, recording inputs of the first

2 and the second S memory registers and the installation inputs of the second and third pulse counters O, the resolution bus 14 is connected to the installation input of frequency divider 6 O and the enable input of the pulse generator 1, the output of which is connected to the summing inputs of the first 8 and second 10 counters pulses, the information output of the second counter 10 is connected to the input of the second register 3 of memory, the second input and the output of the first adder 4 are connected respectively to the output and information input of the third register 12 of memory, and the transfer output to the second input second adder 5, the overflow pulse output of the second pulse counter 10 is connected to the summing input of the third pulse counter 11, the information output of which is connected to the information input of the first memory register 2, the output of which is connected to the first input

Q

.,,

five

the house of the second adder 5, the output of which is connected to the first information INPUT of the comparator unit 7, the output of which is connected to the recording input of the third memory register 12 and the counting input of the frequency divider 6, the installation input of which is connected to the bus 15 for setting the division factor, and the output to the output bus 9 device.

The first adder 4 contains the first 16 and second 17 summation blocks, a code converter 18, first 19 and second 20 inputs, output 21, transfer output 22, first 23 and second 24 code buses, the first 19 and second 20 inputs and the second code bus 24 connected respectively to the first, second and third inputs of the first summation block 16, the output of which is connected to the first input of the second summation block 17, and the transfer output to the transfer output 22 of the first adder 4 and the input of the code converter 18, the output of which is connected to the second input of the second block 17 sum world, whose third input is connected to the first code bus 23, and the output 21 - to the output of the first adder 4 o

The divider works as follows

Before the division begins, counters 8, 10, and 11 and registers 2, 3, and 12 are zeroed out (the initial setup bus is not shown in the diagram). The frequency divider 6 is also in the zero state, since the bus 14 does not have a enable signal.

The input pulse sequence with frequency f is fed to the bus 13. The pulse generator 1 is in standby mode, it can be started only if there is a enable signal on the bus 14 "

After giving the resolution signal, the first pulse of the input sequence with its trailing edge starts generator 1. Generator 1 pulses with frequency F greater than the input frequency f begin to flow to the summing inputs of counters 8 and 10, since both inputs of the comparison unit 7 are equal to one to another (zero) values, the signal from its output is set to O in the counter 8 and the latter does not count the pulses of the generator 1.

The capacitance of the counter 10 is equal to -1, where B is the base of the number system in which the value of the division factor is set, n is the number of bits in the fractional part of the division factor (in particular, for the binary number system B 2, and for the decimal number B 10). Thus, each pulse of the frequency sequence of generator 1 will cause an overflow of counter 10 and adding one to the contents of counter 11

The next impulse received on bus 13 will rewrite the contents of counters 10 and II, respectively, into registers 3 and 2, and the falling edge will reset these counters (meaning that the potential inputs of the O device are connected to the output of a short negative , pulse, shaping on the trailing edge of the input pulse). The number of pulses received from the generator I output during one period t of the input pulse sequence is equal to N t B + C, where m is the number of overflows of the counter 10; .

Thus, in registers 2 and 3, the values m and C will be written, respectively.

The chain consisting of registers 3 and 12 and adder 4 is designed to perform the operations: C + iC (i + l) C, where, 1, 2, 3 „„ o

Adder 4 is organized so that when the sum of the values of registers 3 and 12 exceeds the value equal to B –I, B is subtracted from this sum, and the transfer output of adder 4, which is connected to the second input of bit 2 of adder 5, goes to the active state, what will mean the addition of units to the value of m, received in the adder 5. out of register 2

Thus, the value of C is the fractional part of the number written in the positional number system with base B

Consider the operation of the adder 4.

Summation blocks 16 and 17 have the same capacitance, which exceeds the value of B. Bus 23 is fed direct code to, and bus 24 is supplied with an additional code. Converter 18 codes forms on the output

the code when the adder 16 overflows and an active level appears at its carry output. The code converter 18 does not have its own design and is a purely wiring connection of the transfer output of the first summation block 16 with the corresponding

0 are the input bits of the second summation block 17 and denote the sum of codes arriving at the first Ti second inputs of the adder 4 (i.e., the inputs 19 and 20) by the letter S. As long as the condition

5, a code equal to S + B is generated at the output of the first summation block 16, and at the output of the second summation block 17 -. When a condition arises, the amount

0 S and VdO codes will cause the first summation block 16 to overflow and a code equal to S-B will be generated at its output, and the output level at the transfer output of the adder 4 is Sum

5 codes arriving at the inputs of the second summation block 17 will be equal to 5-in - -Vd5p + B, which means that a code equal to that which corresponds to the operation algorithm is generated at its output

0 adder 4. In the case of setting the division factor in the binary number system, adder 4 is a conventional adder with a capacity of B -1.

five

For time, equal t ,, - koliv

the number of pulses received at the input of the counter 1 will depart N N C

 5 ™ 1

in this expression, the quantities m and -t;

P

are integer and fractional, respectively, parts of the number N. If we bear in mind that in the positional system of number 5 with base B, the values (

-f; And C have the same digital

image, this means that in registers 2 and 3 there will be recorded a whole and fractional part of the number Np, respectively.

The frequency division of the pulses begins after setting the resolution on the bus 14 from the moment of the arrival of the second

5 according to the pulse count of the input sequence. Since in register 2 the number t is written, the output of the comparison unit 7 goes into the passive state and ceases to hold in the zero state.

71529

state 8, which begins to count the pulses of the generator 1.

Block 7 compares the current value of the counter 8 with the value of m. If these values are equal, the output of the comparison block 7 goes to the active state, which resets the counter 8 and overwrites the information Q from the adder 4 to the register 12o. Then a new comparison cycle is performed in block 7 o The current value of the counter 8 will be compared with the values of m or m + 1 depending on the state of the transfer output of the adder 4. This means that at the output of the comparator unit 7, pulses appear after a time equal to

t, .m t - T - t;

or

 1sr

t; T (CNj-H) T (m + l) to -T. -t-t

t, + T (1- IK),

where T is the period of the pulse sequence coming from the output of the generator 1; NJ m is the whole part of the number N.

Calculate the average value of t, the pulse following period at the output of comparison unit 7.

During the time t of the period of the input pulse sequence, the output of this circuit will be formed exactly in pulses, next with a time interval t, or t,. In this case, () Pulses will follow at intervals t, and C pulses - at intervals t; ,) + t; c

t.

C) + T (m + l) C

AT

T (t + -).

h

AT

On the other hand, in the ideal case, the outputs at the output of the comparison circuit 7 should follow the period

, I.N IshvChs .g (w.5-), in to in

Thus, t during the time t of the period of the following impulses, In the particular case when ti t {t ,,

Impulses from the output of the comparison block 7 are fed to the counting input delhi

Q

five

18

telch (t h of the goth, which is in the operating mode, since the permit signal is set on the pin 14,

The division factor of frequency divider 6 is set from the 15o bus. In fact, the fractional division factor K arriving at bus 15 is perceived as an integer number К Кдр-В.

Thus, at the output of the frequency divider 6, Toe ,, on the output bus 9 of the device, a pulse sequence with a period of

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er

ychk ticf to - to to

0

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ABOUT

0

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0

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f, f The frequency of the pulses at the output is equal to

:

BM) i t device

The software divides the frequency f of the input pulses by a predetermined fractional coefficient Kdr.

For a given n, the condition F f -B must be satisfied.

Obviously, the division accuracy increases with increasing frequency F.

The maximum absolute error of the device is equal to the period T of the pulse sequence of the generator 1 o

To compare the above described and known devices, consider a specific example of dividing by the coefficient

9 K 7 1.8 given in the description

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known device. The cd is specified in the decimal number system.

Let in one period of the input pulse sequence fit 64 periods of the frequency sequence of the pulse generator about 64 is the result of raising to the power of the number 2, which is the most favorable case for the known device.

For the example in question, The lanyard consists of approximately 15–17 of the 155 series of microcircuits (the pulse generator 1 is not taken into account). In the known device, only one controlled

The phase shifter 16, consisting of chains with 64 elements of the same type, will contain approximately 35 packages of 155 series microcircuits. Block 6 code comparison, consisting of such chains, even without taking into account elements 5

Comparison will contain approximately 33 cases of 155 series chips

In the case when, in one period of the input sequence, the number of generator pulses is not equal to 2, where, 1,2, 3, .., the known device is even more complicated due to the complexity of block 3 of adders and elements 36,

So, the divider described above is much simpler known, and this advantage will be the greater, the greater the number of generator pulses placed in one period of the input frequency sequence.

Another advantage of the described divider is that it allows dividing the frequency of pulses by a factor of 4) smaller than one, i.e. the output of the divider will appear pulses with a frequency greater than the input. This means that the described divider can work as a pulse frequency multiplier.

Claims (2)

1. A pulse frequency divider with a fractional division factor, comprising a pulse generator, first and second memory registers, first and second adders, a frequency divider, a comparison unit, a first pulse counter and an output bus, the information output of the second memory register connected to the first the input of the first adder, the second input and the output of the comparator unit are connected, respectively, with the information output and the installation input zero of the first pulse counter, characterized in that, in order to extend the range of variation to effitsi- cient dividing by providing a divide-by factor less than unity while simplifying divider, it entered the second and third pulse counters, the third register the memory, the input bus, the resolution bus, and the dividing ratio reference bus, the input bus being connected to Q five 0 5 0 Q g five 0 the start input of the pulse generator, the write inputs of the first and second memory registers and the installation inputs of the second and third pulse counters, the resolution bus is connected to the installation input of the frequency divider and the resolution input of the pulse generator, the output of which is connected to the summing inputs of the first and second counters pulse, the information output of the second pulse counter is connected to the input of the second memory register, the second input and the output of the first adder are connected respectively to the output and information input t There is a memory register and a transfer output is connected to the second input of the second adder, the overflow output of the second pulse counter is connected to the summing input of the third pulse counter, the information output of which is connected to the information input of the first memory register, the output of which is connected to the first input of the second adder, the output of which is connected to the first information input of the comparison unit, the output of which is connected to the recording input of the third memory register and the counting input of the frequency divider, the setting input th coupled to bus specifying dividing ratio and output - with output line divider. 2. The frequency divider according to claim 1, T is characterized in that the first adder contains the first and second summation blocks, the code converter, the first and second code buses, the first, second and third inputs of the first summation block being connected respectively to the first and second the inputs of the first adder and the second code bus, the output of the first summation block is connected to the first input of the second summation block, and the transfer output is connected to the transfer output of the first adder and the input of the code converter, the output of which is connected to the second input of the second th summation unit, the third input of which is connected to the first code bus, and the output is connected to the output of the first adder e one f ( sixteen five L // (puff.Z Editor A.Makovska Compiled by L.Kpevtsova Tehred M.DYdyk Proofreader L. Patay Order 7760/56 Circulation 884 VNIIPI State Committee for Inventions and Discoveries at the State Committee on Science and Technology of the USSR 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and Publishing Combine Patent, Uzhgorod, st. Gagarin, 101 24 22 f f Subscription