JPH01140493A - Mos type dynamic ram - Google Patents

Abstract

PURPOSE:To increase the operating margin of a sense amplifier and to reduce the scale of the voltage supply circuit of a word line by respectively inserting a transistor between input and output ends of a bit line and the sense amplifier. CONSTITUTION:Between a memory array 1 and the amplifier 3, a first N channel MOS type transistor Q1 having a drain connected to the first corresponding bit line B1, a source connected to the first input/output end of the corresponding sense amplifier 3 and a source voltage Vcc to a gate and a second N channel MOS type transistor Q2 having a drain connected to the second corresponding bit line B2, a source connected to the second input/output end of the corresponding sense amplifier 3 and the source voltage Vcc to a gate are disposed. Accordingly, the potential differences between voltages VB1, BB2 of the bit lines B1, B2 and an intermediate potential VMD have the absolute value thereof substantially equal. Thereby, the operating margin of the sense amplifier 3 can be increased and the scale of the word line voltage supply circuit can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an MO8 type dynamic RAM, and particularly to a MOS type die-chemi RAM having a function of precharging a bit line to an intermediate potential when not writing or reading.

[Conventional technology]

Conventionally, the MO8'H3 dynamic RAM in this building has each had one N-channel MO8 type transistor (QMI, QM2) and one capacitor, as shown in FIG.
A plurality of memory cells (MC,, MC2) arranged in a matrix with 1i1i children (Cy1*0M2)
and a plurality of first and second bit lines (Bl, B2) and word lines (Wl) connected to these memory cells.

Wt), and the first and second bit lines (B!.

Bz)k A bit line intermediate potential generation unit 2 precharging to the same intermediate potential and a P-channel MO8 type transistor Q8! , Q82 and N-channel MO8 type transistors Qsa, Qs4.
) to connect these first and second bit lines (Hl,
The configuration includes a plurality of flip-flop differential amplification type sense amplifiers 3 that amplify the potential difference between B2) and a sense amplifier driver 4 that drives the sense amplifiers 3 during writing and reading.

Next, the operation of this MO8 type dynamic RAM will be explained.

FIG. 6 is a waveform diagram of signals of various parts of the MOS type die-chemistry RAM shown in FIG. 5.

Initially, bits mBx and Bz are precharged to an intermediate potential VMD" between power supply voltage VOO and ground potential (OV).

When one word line W1 is selected during reading, and the voltage VWI' of this word aWt rises, the memory cell MC
! Transistor QMI of memory cell MC becomes conductive, bit line B1 and capacitive element CMI of memory cell MC become thin, and memory cell MC! is high-level data.

The voltage VBI on line B becomes slightly higher.

Next, when the activation signal Φ1 to the sense amplifier drive circuit 4 rises, voltages 81 and v82 are supplied to the sense amplifier 3, and the sense amplifier 3 increases the potential difference between the bit lines B1 and 82 and outputs do.

Here, a voltage higher than the power supply voltage VOO is applied to the word lines W and K, and therefore the voltage VMI at the connection point (hereinafter referred to as node Nl) between the transistor QM1-' of the memory cell MCI and the capacitive element CMI is equal to the bit line. Bl
The voltage VBIK follows and rises to the power supply voltage VOO.

In this way, memory cell MC! is refreshed.

Next, the word line W! When the voltage of the activation signal 0 falls and the activation signal Φ2 to the bit line intermediate potential generating section 2 rises, the bit line intermediate potential generating section 2 causes the Q bit line B!
, B2 are recharged to the intermediate potential VMD" in preparation for the next read/write.

The voltage of the bits ad, , B2 is the voltage of the memory cells MC1, , B2.
Whether the data of MC2 is at a high level or a low level, the same intermediate potential VMD is obtained.

That is, the bit line intermediate potential generation section 2 generates the bit line B+,
It has a B2'e balancing function.

[Problem that the invention seeks to solve]

As mentioned above, in the conventional MO8 type dynamic RAM, the voltage Vwl of the word rfA (Wl, Wz) at the time of selection is
', 2W2' Since the voltage is higher than the total power supply voltage VOO, there is a drawback that the voltage supply circuit to word a (Wt 2 , Wt 2 ) becomes large and the control becomes complicated.

On the other hand, if the voltage of the word line (Wl, Wz) at the time of selection is set to the same level as the power supply voltage Vco, as shown in FIG. 7, the node N! The difference between the voltage VMI and the intermediate potential VMD is smaller when the data is at a high level due to the threshold voltage of the transistor QMI, and becomes larger when the data is at a low level. It has the disadvantage that it decreases.

An object of the present invention is to provide a simple configuration even when the voltage of the word line at the time of selection is set to the same level as the total power supply voltage, and the first and second bits when the data of the memory cell is at a high level and when it is at a low level. An object of the present invention is to provide an MO8 type dynamic AMi that can balance the potential difference with respect to the line intermediate potential, thereby increasing the operating margin of a sense amplifier and reducing the scale of a word line voltage supply circuit.

[Means for solving all problems] The uninvented MO8 type dynamic AM has a plurality of memory cells arranged in a matrix, a plurality of first and second bit lines and word lines connected to these memory cells. a bit line intermediate potential generating section that precharges the first and second bit lines to the same intermediate potential during periods when no writing or reading is performed; The gates are connected to the corresponding bit lines 1 and held at a predetermined potential, and the drains (or sources) of the plurality of transistors 1 are connected to the corresponding second bit lines, and the gates are held at a predetermined potential. a plurality of second transistors held at a potential of
A free-lag flop that connects to the second input/output terminal (or drain) and connects to the source (or drain) of the corresponding transistor of name 2 and amplifies the entire potential difference between the corresponding first and second bit lines. It has a plurality of differential boost type sense amplifiers.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In this embodiment, the conventional MO8 type shown in Figure 1@5 is connected to the corresponding first bit line (Bl), the source is connected to the first input/output terminal of the corresponding sense amplifier 3, and the gate is connected to the first input/output terminal of the corresponding sense amplifier 3. A plurality of N-channel MO8-type first transistors (Ql) are connected to the power supply voltage VOO, and their drains are connected to the corresponding second bit lines (B2), and their sources are connected to the second transistors of the corresponding sense amplifiers 3. Multiple N-channel MOs connected to the input/output terminals and connected to the power supply voltage ■oot' to the gates
The second transistor (Q2) of type 8 and the full role are at the intersection.

The operation of this embodiment will be explained below.

Figure iK2 is a waveform diagram of the signals of the t-th parts, which explains the entire operation of this embodiment.

When word line W1 is selected during reading, etc., and voltage VWI of word line W1 rises, memory cell MC1 and bit line B1 are coupled, and activation signal Φ! rises, the sense amplifier 3 receives the voltage V81. V82 is supplied and the sense amplifier 3 goes to the bit line H! , 82 is fully amplified and output.

Here, the voltage VOI at the first input/output terminal of the sense amplifier 3 rises to the power supply voltage VOC when the data of the memory cell MC is at a high level, but the voltage VOI at the first input/output terminal of the sense amplifier 3 rises to the power supply voltage VOC, but the voltage VOI at the first input/output terminal of the sense amplifier 3 rises to the power supply voltage VOC. 'If pressure is transistor Q! The threshold voltage of the power supply voltage VOO
It will only rise to a voltage one step lower.

Node N! The voltage VMI follows the voltage VB□ of the bit line B1.

Next, when the activation signal Φ2 rises and the bit line intermediate potential generating section 2 operates, the voltage VBI of the bit lines B, ,B,
It becomes an intermediate potential VMD between a voltage balanced with VB2 and one level lower than the power supply voltage VOO and the ground potential.

Therefore, the voltage at the node Nl is only one step lower than the power supply voltage VOO, but the voltage on the bit lines Bl and B2 is VB!
, ■ The absolute value of the potential difference between B2 and the intermediate potential VMD is almost the same whether the data in the memory cell is at a high level or a low level. , and low levels can be made the same, thus increasing operating margin.

FIG. 3 is a circuit diagram showing a second embodiment of the invention.

In this embodiment, the first and second transistors Ql +Q
2 is supplied to the gate voltage generation circuit 5,
This gate voltage can be changed arbitrarily.
It is something.

By changing this gate voltage, bit line Br
, Bz 17)' can be set to the voltage Vnt and VB2 to the maximum potential VMD'. As miniaturization progresses, the capacity of memory cells (Met, MCz) i: element < CMx
, CN3) becomes thinner, so the withstand voltage characteristics of this oxide film decreases, but by applying all of these examples, the voltage between the electrodes of the capacitive element (CMI, CN3) can be lowered. There is an advantage that it can be done.

〔Effect of the invention〕

As explained above, by configuring transistors to be inserted between the bit line and the input/output terminal of the sense amplifier, the word line voltage at the time of selection can be easily made to the same level as the total power supply voltage. With this circuit, it is possible to make the potential difference between the voltages of the first and second bit lines and the intermediate potential to be the same when the data of the memory cell is at a high level and at a low level, and therefore the operation of the sense amplifier is This has the effect of increasing the margin and reducing the scale of the word line voltage supply circuit.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, FIG. 2 is a waveform diagram of signals of each part to explain the operation of the embodiment shown in FIG. FIG. 4 is a circuit diagram showing the second embodiment. FIG. 4 is a waveform diagram of the signals of each part for explaining the operation of the embodiment shown in FIG. 3. FIG.
A circuit diagram showing an example of type dynamic 9 AM, FIGS. 6 and 7 are MO8 type dynamic RA shown in FIG.
FIG. 4 is a waveform diagram of signals of various parts for explaining the operation of M. DESCRIPTION OF SYMBOLS 1...Memory array, 2...Bit rest intermediate potential generation section, 3...Sense intensifier, 4...Sense intensifier driver, 5...Gate voltage generation circuit s Bl + 82
...bit line, CMI, 0M2...answer element,
MCI, MC2...Memory cell, Ql eQs #Q
M1 eQvz*Qs]~Qs4-h transistor, W
l, W2...word line. Agent Patent Attorney Uchihara Former Time Figure 2 Time Figure 6 Time Figure 1 Figure 7

Claims (1)

[Claims] A memory array comprising a plurality of memory cells arranged in a matrix, and a plurality of first and second bit lines and word lines connected to these memory cells; and a bit line intermediate potential generation unit that precharges the second bit line to the same intermediate potential;
a plurality of first transistors each having a drain (or source) connected to the corresponding first bit line and having a gate held at a predetermined potential; and a plurality of first transistors each having a drain (or source) connected to the corresponding second bit line. a plurality of second transistors whose gates are held at a predetermined potential; and a plurality of second input/output terminals each having a first input/output terminal connected to the source (or drain) of the corresponding first transistor; and a plurality of flip-flop differential amplification type sense amplifiers connected to the sources (or drains) of the corresponding second transistors and amplifying the potential difference between the corresponding first and second bit lines. Characteristic MOS type dynamic RAM.