JPH01140246A - Logic simulator - Google Patents

Abstract

PURPOSE:To automatically set a stop time during an action by providing a counter to add or subtract a fixed value for each clock and comparator to judge whether a value held by the counter is a prescribed value or not and stopping a simulation when the comparator judges that the held value of the counter is the prescribed value. CONSTITUTION:When a certain fact occurs while executing a logic simulation and the execution of the logic simulation is stopped by the result, the output of a decrementor 2 and the input of comparator 3 are connected by a connecting line 8 by a decrementor comparator preparing part 1. By this connection, the comparator 3 compares the input of the decrementor 2 with 0, next, the number of clocks is loaded into the decrementor 2 through a load part 4 and a simulation reopening command is generated from a simulation control part 5. A simulation part 6 reopens the simulation, the decrementor 2 subtracts for each clocks, 0 is judged by the comparator and supplied to the control part 5 and an action stop instruction is outputted in response to this.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a logic simulator.

(Conventional technology) In traditional logic simulators, ・Stop when a certain signal reaches a specified state value.

- Specify the number of clocks or patterns when starting the simulator, and stop after performing the specified number of simulations.

(Japanese Patent Application No. 61-185931. Information Processing October 1984 issue PIθ48-P1055 Simulator).

[Problem that the invention seeks to solve]

With the conventional logic simulators mentioned above, it is not possible to dynamically specify a stop during simulation, and it is not possible to specify a stop at multiple different times at once. (Interrupt processing from the logic circuit to be verified to the I10 device, etc.)
If it is necessary to carry out post-processing (such as writing the contents read from the I10 device to the memory of the logic circuit to be verified) after a certain time, if the above event occurs irregularly, the post-processing may be performed after a certain time. This method has the disadvantage that it is not possible to specify the stop of the simulation necessary to perform the simulation.

Means for Solving Problem C] The logic simulator of the present invention includes a counter that subtracts or adds a fixed number every clock, and a comparator that determines whether the value held by the counter is a predetermined value. , means for creating on a simulation model when a certain simulation condition is met and the simulation is stopped; means for setting an initial value in the counter and operating the counter when a simulation restart command is issued; and the comparison method. and means for stopping the simulation when the value held by the counter is determined by the device to be the predetermined value.

[For production]

Therefore, the stop time can be dynamically specified during simulation.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the logic simulator of the present invention.

The decrementer/comparator creation unit 1 changes the simulation model 71 to a simulation model 72. The simulation model 71 and the simulation model 72 include a decrementer 2 and a comparator 3.

On the simulation model 71, the comparator 3 indicates a mismatch. The operation procedure of the simulation section 6 is controlled by the simulation control section 5. The loading section 4 has a function of loading the clock number into the decrementer 2. The simulation control unit 5 has a function of stopping execution of the logic simulation when the comparator 3 indicates a match. In this embodiment, three sets of comparators 3 and decrementers 3 are provided so that three simulation stop times can be set, but of course, a - set may also be used.

In such a configuration, during execution of logical simulation,
When a certain fact occurs and, as a result, the execution of the logic simulation is stopped, the decrementer/comparator creation unit 1 connects the output of the decrementer 2 and the input of the comparator 3. This connection is made by a connecting line 8. As a result, the comparator 3 compares the output of the decrementer 2 with "0". Next, the clock number is loaded into the decrementer 2 through the loading section 4. When a simulation restart command is issued by the simulation control unit 5 and the simulation unit 6 restarts the logic simulation, the decrementer 2 is decremented every clock. When the logic simulation is executed for the number of clocks, the comparator 3 determines that the value of the decrementer 2 is O. This judgment is supplied as a judgment signal to the simulation control section 5, and in response, the simulation control section 5 sends a simulation operation stop command to the simulation section 6. With this, even if another event occurs during execution of a logical simulation, you can similarly specify the stop of the simulation by the number of clocks. Furthermore, by predefining the number of locks to be executed for each event, it is possible to dynamically specify a stop during simulation execution.

Note that the value compared by the comparator 3 does not have to be 0, and an incrementer may be used instead of the decrementer 2.

〔Effect of the invention〕

As explained above, the present invention provides an output stage that creates a counter that subtracts or adds a certain number every clock and a comparator that determines whether the value held by the counter is a predetermined value on a simulation model; By providing a logic simulator with means for setting an initial value in the counter and means for stopping the simulation when the comparator determines that the value held by the counter is a predetermined value, the stop time can be changed during simulation. There are effects that can be set.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the logic simulator of the present invention. 1...Decrementer/comparator creation section, 2...
...Decrementer, 3---Comparator, 4...
...Load section, 5...Simulation control section, 6------
・Simulation department, 71------ Simulation model, 72---
---Simulation model, 8... Connection line.

Claims (1)

[Claims] In a logic simulator, a counter that subtracts or adds a fixed number every clock;
means for creating a comparator for determining whether the value held by the counter is a predetermined value on a simulation model when a certain simulation condition is satisfied and the simulation is stopped; and setting an initial value for the counter. and means for operating the counter when a simulation restart command is issued; and means for stopping the simulation when the comparator determines that the value held by the counter is the predetermined value. A logic simulator featuring: