JPH01135099A - Electronic circuit package - Google Patents

Electronic circuit package

Info

Publication number
JPH01135099A
JPH01135099A JP29437687A JP29437687A JPH01135099A JP H01135099 A JPH01135099 A JP H01135099A JP 29437687 A JP29437687 A JP 29437687A JP 29437687 A JP29437687 A JP 29437687A JP H01135099 A JPH01135099 A JP H01135099A
Authority
JP
Japan
Prior art keywords
electronic circuit
wiring board
circuit package
printed wiring
face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29437687A
Other languages
Japanese (ja)
Inventor
Shinji Takahashi
伸治 高橋
Sunao Sugiyama
直 杉山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ibiden Co Ltd
Original Assignee
Ibiden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibiden Co Ltd filed Critical Ibiden Co Ltd
Priority to JP29437687A priority Critical patent/JPH01135099A/en
Publication of JPH01135099A publication Critical patent/JPH01135099A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Abstract

PURPOSE:To realize an electronic circuit package having high reliability and high universality even if an adverse influence of a large electromagnetic wave noise by forming a conductor film having no signal line at least on end face of a both-side or multilayer wiring board having a terminal for electrically connecting a component placing face to an exterior. CONSTITUTION:An electronic circuit has a structure surrounded by inner layer conductors 7, 8 of the power line of a multilayer printed wiring board 3, and an end face shielding pattern 5 made of a conductive material electrically connected to the conductors 7, 8. Accordingly, it can prevent an electromagnetic wave noise from invading to the electronic circuit block from an exterior and from radiating from the electronic circuit block to the exterior.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は、電子回路パッケージに関するものであり、特
にその内部に形成される電子回路を外部の電磁波ノイズ
からシールドし、また内部の電子回路の電磁波ノイズか
外部へ放射されるのをシールドする電子回路パッケージ
に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an electronic circuit package, and in particular to shielding an electronic circuit formed inside the package from external electromagnetic noise, and shielding the electronic circuit inside the package. This invention relates to an electronic circuit package that shields electromagnetic noise from being radiated to the outside.

（従来の技術） 近年の電子回路技術の発達により、所謂半導体素子等の
電子部品の集積度は相当高度になってきている。このた
め自動傘、産業用機器等においても種々の電子機器が搭
載され、また各電子部品の動作も高速になってきている
。このため産業用機器に設置される電子機器においては
、安全上、機器外部の電磁波ノイズの影響をうけないよ
う確実にシールドする必要がある。また、デジタル回路
とアナログ回路もマイクロコンピュータやセンサ技術の
発達に伴い、混在してより高度な動作をするようになっ
てきたが、特にアナログ回路は他の電子回路からの干渉
を受は易いので確実にシールドする必要があることは勿
論、デジタル回路にあっても確実にシールドし、他の回
路を干渉しないようにする必要がある。(Prior Art) With the recent development of electronic circuit technology, the degree of integration of electronic components such as so-called semiconductor devices has become considerably high. For this reason, various electronic devices are being installed in automatic umbrellas, industrial equipment, etc., and the operation of each electronic component is also becoming faster. Therefore, for safety reasons, electronic devices installed in industrial equipment must be reliably shielded from being affected by electromagnetic noise from outside the device. Furthermore, with the development of microcomputers and sensor technology, digital circuits and analog circuits have come to coexist and perform more sophisticated operations, but analog circuits are especially susceptible to interference from other electronic circuits. Not only does it need to be reliably shielded, but even digital circuits need to be reliably shielded to prevent interference with other circuits.

そこで従来においては、シールド用の金属製の箱内に各
電子機器を設置したり、また電子機器の各回路を金属板
で形成したブロック内に設けることによりシールドし、
さらに電源部、デジタル回路、アナログ回路等をお互い
にできるたけ離して配置するようにしていた。Therefore, in the past, each electronic device was shielded by installing it in a metal box for shielding, and each circuit of the electronic device was installed in a block made of a metal plate.
Furthermore, the power supply section, digital circuits, analog circuits, etc. were placed as far away from each other as possible.

ところが、従来の方法では、シールド用の金属製の箱や
金属板の体積及び重量がかさみ、また目的とするプリン
ト配線板ごとに専用の金属製の箱や金属板が必要となる
欠点があった。However, the conventional method has the disadvantage that the volume and weight of the metal box or metal plate for shielding increases, and that a dedicated metal box or metal plate is required for each target printed wiring board. .

また、同一プリント配線板上でアナログ回路とデジタル
回路とを隣り合せるように配置し、省スペース化を達成
することが困難であった。Furthermore, it has been difficult to arrange analog circuits and digital circuits next to each other on the same printed wiring board to save space.

さらに、ただキャップのみを電子回路パッケージにのせ
るだけでは、完全なシールド効果をあげることは困難で
あった。Furthermore, it is difficult to achieve a complete shielding effect by simply placing a cap on an electronic circuit package.

（発明が解決しようとする問題点） 本発明は、以上のような経緯からなされたもので、その
解決しようとする問題点は、従来の技術における電磁シ
ールド化の不足である。(Problems to be Solved by the Invention) The present invention has been made in view of the above-mentioned circumstances, and the problem to be solved by the present invention is the lack of electromagnetic shielding in the conventional technology.

そして、本発明の目的とするところは、簡単な構成てあ
って、従来技術を充分利用・発展させることができ、し
かも必要とされる電磁シールドが可能な電子回路パッケ
ージを提供することにある。すなわち本発明の目的は、
電磁シールド化を可能とした電子回路パッケージを用い
て、デジタル回路、アナログ回路の混在を可能とし、さ
らには電磁波ノイズの大きい悪影響のもとでも高い信頼
性のある汎用性の高い電子回路パッケージを実現するこ
とである。It is an object of the present invention to provide an electronic circuit package which has a simple structure, allows sufficient use and development of the prior art, and is capable of providing the required electromagnetic shielding. That is, the purpose of the present invention is to
By using an electronic circuit package that enables electromagnetic shielding, it is possible to mix digital and analog circuits, and even under the adverse effects of large electromagnetic noise, we have created a highly reliable and versatile electronic circuit package. It is to be.

（問題点を解決するための手段） 以上の問題点を解決するために本発明が採った手段は、
第１ＵＡ及び第２図を参照して説明すると、 ｒ電子部品が表面実装などによって実装される部品ｇａ
而と外部とを電気的に接続するための端子とを有する１
両面、或いは多層の配線板の少なくとも端面に、信号線
に使用しない導体膜を形成したすることを特徴とする電
子回路パッケージ１である。(Means for solving the problems) The means taken by the present invention to solve the above problems are as follows:
To explain with reference to UA 1 and FIG. 2, r electronic components are mounted by surface mounting etc.
1 having a terminal for electrically connecting the body and the outside;
This electronic circuit package 1 is characterized in that a conductive film not used for signal lines is formed on both sides or at least the end face of a multilayer wiring board.

次に、本発明を図面に基づいて詳細に説明する。Next, the present invention will be explained in detail based on the drawings.

第１図は１本発明の一実施例である電子回路パッケージ
（１）に電子部品（２）を実装した状態の斜視図であり
、この電子回路パッケージ（１）は、多層プリント配線
板（３）、導体ビン（４）、電子部品（２）、及び端面
に形成した信号線に使用しない導体ｆｆ（５）　　（以
下、端面シールドパターン（５）と略す）によって構成
されている。第２図は、第１図の部分拡大断面図で”あ
る、このうち多層プリント配線板（３）の裏面側には、
多層プリント配線板（コ）の電源ラインである内層導体
（７）（８）と電気的に接続されたスルーホール（９）
が設けられている。一方、端面シールドパターン（５）
は導電性材料によって形成されており、多層プリント配
線板（３）の側面を完全に覆い、尚かつ裏面シールドパ
ターンとも電気的に接続されている。FIG. 1 is a perspective view of an electronic circuit package (1), which is an embodiment of the present invention, in which an electronic component (2) is mounted. ), a conductor bottle (4), an electronic component (2), and a conductor ff (5) that is not used for the signal line formed on the end face (hereinafter abbreviated as the end face shield pattern (5)). Figure 2 is a partially enlarged sectional view of Figure 1.On the back side of the multilayer printed wiring board (3),
Through-holes (9) electrically connected to the inner layer conductors (7) and (8), which are the power lines of the multilayer printed wiring board (co).
is provided. On the other hand, the end shield pattern (5)
is made of a conductive material, completely covers the side surfaces of the multilayer printed wiring board (3), and is also electrically connected to the back shield pattern.

（発明の作用） 第２図に示される如く、電子回路が多層プリント配線板
（３）の電源ラインである内層導体（７）（１３）と、
この内層導体（７）（＋１）に電気的に接続された導電
性材料を使用した端面シールドパターン（５）とにより
囲まれた構造を有しているため、外部からのこの電子回
路ブロックへの電磁波ノイズの侵入や、外部へのこの電
子回路ブロックからの電磁波ノイズの放射を防ぐことが
出来る。(Function of the invention) As shown in FIG. 2, the electronic circuit includes inner layer conductors (7) and (13) which are power supply lines of the multilayer printed wiring board (3);
Since it has a structure surrounded by an end face shield pattern (5) using a conductive material that is electrically connected to the inner layer conductor (7) (+1), there is no interference from the outside to this electronic circuit block. It is possible to prevent the intrusion of electromagnetic noise and the radiation of electromagnetic noise from this electronic circuit block to the outside.

また、本発明に加えて両面プリント配線板（３）の裏面
にシールドパターンを形成することにより１両面プリン
ト配線板を用いてもより良好なシールド効果が得られる
。Further, in addition to the present invention, a better shielding effect can be obtained even when a single-sided printed wiring board is used by forming a shield pattern on the back surface of the double-sided printed wiring board (3).

また、端面シールドパターン（５）を形成することによ
り、従来の電子回路パッケージに比べ、水分の侵入断面
積を減少させ、プラスチックバラケージの課題である吸
水防ＩＦに効果を発揮する。Furthermore, by forming the end face shield pattern (5), the cross-sectional area of moisture intrusion is reduced compared to conventional electronic circuit packages, and it is effective in preventing water absorption IF, which is a problem for plastic cages.

（実施例） 次に、本発明を図面に示した実施例に基づいて詳細に説
明する。(Example) Next, the present invention will be described in detail based on an example shown in the drawings.

実施例１ 板厚１．１ｍｍのガラス−エポキシ銅張積層板（両面銅
箔７０　）ｈ　ｍ　）に、通常のサブトラクティブ法に
て内層導体回路（７）（８）を形成した後、ガラス−エ
ポキシプリプレグ（０，２ｍｍ厚）を用いて厚み１８４
ｍの銅箔をプレス法により張り合わせ、多層基板を形成
した。さらに、この多層基板に、第１スルーホール（９
）を形成するための貫通孔と、第２スルーホール（１２
）を形成するための非貫通孔とを設け、さらに端面シー
ルドパターン（５）を形成するための打ち抜き加工を施
した。これに無電解及び電解銅メツキを施し、スルーホ
ール（９）（１２）及び外層導体回路（１０）（１１）
の形成を行った後、外形加工を行い、端面シールドパタ
ーン（５）を有した多層プリント配線板（３）音形成し
た。そして、この多層プリント配線板（３）の第２スル
ーホール（１１）に、半田メツキを施したコバール袈の
導体ピン（４）を高融点半田デイツプ法により固定して
、電子回路パッケージ（１）を製作した。Example 1 After forming inner layer conductor circuits (7) and (8) by a normal subtractive method on a glass-epoxy copper-clad laminate (copper foil on both sides hm) with a thickness of 1.1 mm, Thickness 184 using epoxy prepreg (0.2mm thickness)
A multilayer board was formed by laminating m copper foils together using a press method. Furthermore, a first through hole (9
) and a second through hole (12
) to form a non-through hole, and further punching was performed to form an end face shield pattern (5). Electroless and electrolytic copper plating is applied to this to form through holes (9) (12) and outer layer conductor circuits (10) (11).
After forming, the external shape was processed and a multilayer printed wiring board (3) having an end face shield pattern (5) was formed. Then, the conductor pins (4) of the solder-plated Kovar cap are fixed to the second through-holes (11) of the multilayer printed wiring board (3) by high melting point solder dip method, and the electronic circuit package (1) is assembled. was produced.

この後、電子部品（２）を半導体素子接続部に半田によ
って固定した。そして、ニッケルめっきが施された銅製
のキャップ（６）を製作し、多層プリント配線板の上面
を完全に覆うように載置した。Thereafter, the electronic component (2) was fixed to the semiconductor element connection portion with solder. Then, a nickel-plated copper cap (6) was manufactured and placed so as to completely cover the top surface of the multilayer printed wiring board.

そして、このキャップ（６）と多層プリント配線板（３
）の端面シールドパターン（５）とを半田付け（１コ）
により電気的に接続した。Then, this cap (6) and the multilayer printed wiring board (3)
) with the end face shield pattern (5) (1 piece)
electrically connected.

このようにして多層プリント配線板（３）の電源ライン
である内層導体（７）（８）と、それに電気的に接続さ
れたキャップ（５）とで囲まれた構造のシールド効果の
高い、第４［３４に示す電子回路パッケージが得られた
。In this way, the inner layer conductor (7) (8), which is the power supply line of the multilayer printed wiring board (3), and the cap (5) electrically connected thereto have a highly shielding effect. An electronic circuit package shown in No. 4 [34] was obtained.

害」ｕ１ス 板厚１．１ｍｍのガラス−エポキシ銅張積層板（両面鋼
箔７０ＩＬｍ）に、通常のサブトラクティブ法にて内層
導体回路（７）（８）を形成した後、ガラス−エポキシ
プリプレグ（０，２ｍｍＪｑ）を用いて、厚み１８ｇｍ
の銅箔をプレス法により張り合わせ、多層基板を形成し
た。さらに、この多層基板に、第１スルーホール（９）
を形成するための貫通孔と、第２スルーホール（１２）
を形成するための非貫通孔とを設け、さらに端面シール
ドパターン（５）を形成するための打ち抜き加工を施し
た。これに無電解及び電解鋼メツキを施し、スルーホー
ル（９）（１２）及び外層導体回路（１０）（１１）の
形成を行った後、外形加工を行い、端面シールドパター
ン（５）を有した多層プリント配線板（３）を形成した
。そして、この多層プリント配線板（３）の第２スルー
ホール（１１）に、半田メツキを施したコバール製の導
体ビン（４）を高融点半田デイツプ法により固定して、
電子回路パッケージ（１）を装作した。After forming inner layer conductor circuits (7) and (8) on a glass-epoxy copper-clad laminate (double-sided steel foil 70ILm) with a thickness of 1.1 mm using the usual subtractive method, glass-epoxy prepreg was (0.2mmJq), thickness 18gm
A multilayer board was formed by pasting the copper foils together using a press method. Furthermore, a first through hole (9) is provided in this multilayer board.
a through hole for forming a second through hole (12)
A non-through hole was provided to form a shield pattern (5), and a punching process was performed to form an end face shield pattern (5). This was subjected to electroless and electrolytic steel plating, through holes (9) (12) and outer layer conductor circuits (10) (11) were formed, and then externally processed to form an end shield pattern (5). A multilayer printed wiring board (3) was formed. Then, a solder-plated conductor bottle (4) made of Kovar is fixed to the second through hole (11) of this multilayer printed wiring board (3) using a high melting point solder dip method.
An electronic circuit package (1) was installed.

この後、ＬＳＩチップをダイボンデインクバッドに接続
し、ワイヤーボンディングを行９た後。After this, the LSI chip was connected to the die bonding pad, and wire bonding was performed in row 9.

エポキシ樹脂にてモールドした。Molded with epoxy resin.

このようにして多層プリント配線板（３）の電源ライン
である内層導体（７）（８）と、それに電気的に接続さ
れた端面シールドパターン（５）とで囲まれた構造のシ
ールド効果の高い、第５図に示す電子回路パッケージ（
１）が得られた。In this way, the shielding effect of the structure surrounded by the inner layer conductors (7) and (8), which are the power supply lines of the multilayer printed wiring board (3), and the end face shield pattern (5) electrically connected thereto is achieved. , the electronic circuit package shown in Figure 5 (
1) was obtained.

実施例３ 板厚１．６ｍｍのガラス−ポリイミド鋼張積層板（両面
銅箔１８Ｂｍ−両面板（１５））に側面スルーホール（
１６）を形成するための貫通孔を設け。Example 3 A side through hole (
16) A through hole is provided to form the hole.

さらに側面スルーホール部を除いて端面シールドパター
ン（５）を形成するための打ら抜き加工を行った。これ
に無電解及び電解鋼メツキを施し。Furthermore, punching was performed to form an end face shield pattern (5) excluding the side through hole portions. This is coated with electroless and electrolytic steel plating.

スルーホール及び外層導体回路（１１）の形成を行った
後、外形加工を行い、側面スルーホール（１６）と端面
シールドパターン（５）と°を有した両面プリント配線
板（１５）を製作した。After forming the through holes and the outer layer conductor circuit (11), the external shape was processed to produce a double-sided printed wiring board (15) having side through holes (16) and end shield patterns (5).

実施例４ 板厚１．１ｍｍのガラス−エポキシ鋼張積層板（両面鋼
箔７０　ｐｍ）に、通常のサブトラクティブ法にて内層
導体回路（７）（８）を形成した後、ガラス−エポキシ
プリプレグ（０，２ｍｍ厚）を用いて、厚み１８ｐｍの
銅箔をプレス法により張り合わせ、多層基板を形成した
。この多層基板に、第１スルーホール（９）を形成する
ための貫通孔と、さらに端面シールドパターンを形成す
るための打ち抜き加工を行なった。これに無電解及び電
解銅メツキを施し、スルーホール及び外層導体回路の形
成を行った後、外形加工を行い、端面シールドパターン
（５）を有した多層プリント配線板（３）を形成した。Example 4 After forming inner layer conductor circuits (7) and (8) on a 1.1 mm thick glass-epoxy steel laminate (double-sided steel foil 70 pm) by a normal subtractive method, glass-epoxy prepreg was formed. (0.2 mm thick) and pasted together a 18 pm thick copper foil by a pressing method to form a multilayer board. This multilayer substrate was punched to form a through hole for forming a first through hole (9) and further for forming an end face shield pattern. This was subjected to electroless and electrolytic copper plating to form through holes and outer layer conductor circuits, and then externally processed to form a multilayer printed wiring board (3) having an end face shield pattern (5).

尚、本実施例では装置設計１、電磁波ノイズの侵入や放
射をシールドする必要のない１つの端面な除き端面シー
ルドパターン（５）は４つの端面の内３つの端面だけに
施した。In this example, in device design 1, the end face shield pattern (5) was applied to only three of the four end faces, except for one end face that does not require shielding from electromagnetic noise intrusion or radiation.

（発明の効果） 以上詳述した通り本発明に係る電子回路パッケージにあ
っては、上記実施例に示した如く。(Effects of the Invention) As detailed above, the electronic circuit package according to the present invention is as shown in the above embodiments.

ｒ電子部品が表面実装などによって実装される部品搭載
面と外部とを電気的に接続するための端子とを有する、
両面、或いは多層の配線板の少なくとも端面に、信号線
に使用しない導体膜を形成したすること」にその構成上
の特徴があり、これにより簡単な構成であって従来の問
題点を解決した電子回路パッケージを提供することがで
きるのである。r having terminals for electrically connecting the component mounting surface on which electronic components are mounted by surface mounting or the like and the outside;
Its structural feature lies in the fact that a conductive film not used for signal lines is formed on at least the end surfaces of a double-sided or multilayer wiring board. It is possible to provide circuit packages.

すなわち、本発明に係る電子部品用シールドパッケージ
にあっては、外部の電磁波ノイズに敏感な回路、電磁波
ノイズを放射しやすい高周波回路を局所的に遮蔽または
アイソレート化し、回路動作を安定化させることにより
、電子回路の信頼性を向−トさせることが出来るととも
に、実装回路を小型化できるのである。さらに耐水性、
耐候性の向上も実現することができる。That is, in the shielded package for electronic components according to the present invention, circuits that are sensitive to external electromagnetic noise and high-frequency circuits that tend to radiate electromagnetic noise are locally shielded or isolated to stabilize circuit operation. As a result, the reliability of the electronic circuit can be improved and the size of the mounted circuit can be reduced. Furthermore, water resistance
Improved weather resistance can also be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明に係る電子回路パッケージを示す斜視図
、第２図は第１図の電子回路パッケージの構成を概略的
に示す部分拡大断面図、第３図は本発明に係る別の電子
回路パッケージを示す斜視図、第４図及び第５図はそれ
ぞれ実施例１及び実施例２に対応する電子回路パッケー
ジを示す部分拡大断面図、第６図及び第７図はそれぞれ
実施例３及び実施例４に対応する電子回路パッケージを
示す斜視図である。 符号の説明 ｌ・−・電子回路パッケージ、２・・・電子部品、３・
・・多層プリント配線板、４−・・導体ピン、５・・・
端面シールドメツキ、６・・・キャップ、７・・・内層
導体、８・・・内層導体、９−・・第１スルーホール、
１０−・・外層導体、ｌｌ−・・外層導体、１２−・・
第２スルーホール、１３−・・半田、１４−・・エポキ
シ樹脂、１５・−両面板、１６−・・側面スルーホール
。FIG. 1 is a perspective view showing an electronic circuit package according to the present invention, FIG. 2 is a partially enlarged sectional view schematically showing the configuration of the electronic circuit package in FIG. 1, and FIG. 3 is a perspective view showing another electronic circuit package according to the present invention. 4 and 5 are partially enlarged sectional views showing electronic circuit packages corresponding to Embodiment 1 and 2, respectively. FIGS. 6 and 7 are sectional views illustrating Embodiment 3 and Embodiment 3, respectively. FIG. 7 is a perspective view showing an electronic circuit package corresponding to Example 4. Explanation of symbols 1--Electronic circuit package, 2--Electronic component, 3-
...Multilayer printed wiring board, 4-...Conductor pin, 5...
End shield plating, 6... Cap, 7... Inner layer conductor, 8... Inner layer conductor, 9-... First through hole,
10-...Outer layer conductor, ll-...Outer layer conductor, 12-...
2nd through hole, 13--Solder, 14--Epoxy resin, 15--Double-sided board, 16--Side through hole.

Claims (1)

【特許請求の範囲】[Claims] 　電子部品が表面実装などによって実装される部品搭載
面と外部とを電気的に接続するための端子とを有する、
両面、或いは多層の配線板の少なくとも端面に、信号線
に使用しない導体膜を形成したすることを特徴とする電
子回路パッケージ。It has a terminal for electrically connecting the component mounting surface on which electronic components are mounted by surface mounting or the like and the outside.
1. An electronic circuit package characterized in that a conductive film not used for signal lines is formed on both sides or at least the end face of a multilayer wiring board.
JP29437687A 1987-11-20 1987-11-20 Electronic circuit package Pending JPH01135099A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29437687A JPH01135099A (en) 1987-11-20 1987-11-20 Electronic circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29437687A JPH01135099A (en) 1987-11-20 1987-11-20 Electronic circuit package

Publications (1)

Publication Number Publication Date
JPH01135099A true JPH01135099A (en) 1989-05-26

Family

ID=17806919

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29437687A Pending JPH01135099A (en) 1987-11-20 1987-11-20 Electronic circuit package

Country Status (1)

Country Link
JP (1) JPH01135099A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0421343A3 (en) * 1989-10-03 1993-03-17 Matsushita Electric Industrial Co., Ltd. Semiconductor element package and semiconductor element package mounting distributing circuit basic plate
JPH08288686A (en) * 1995-04-20 1996-11-01 Nec Corp Semiconductor device
JPH0964580A (en) * 1995-08-22 1997-03-07 Nec Corp Hybrid integrated circuit device and production thereof
JPH09232721A (en) * 1996-02-28 1997-09-05 Hitachi Aic Inc Printed wiring board manufacturing method
US5886876A (en) * 1995-12-13 1999-03-23 Oki Electric Industry Co., Ltd. Surface-mounted semiconductor package and its manufacturing method
WO2007116657A1 (en) * 2006-04-10 2007-10-18 Panasonic Corporation Relay substrate, method for manufacturing the relay substrate and three-dimensional circuit device using the relay substrate

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0421343A3 (en) * 1989-10-03 1993-03-17 Matsushita Electric Industrial Co., Ltd. Semiconductor element package and semiconductor element package mounting distributing circuit basic plate
JPH08288686A (en) * 1995-04-20 1996-11-01 Nec Corp Semiconductor device
JPH0964580A (en) * 1995-08-22 1997-03-07 Nec Corp Hybrid integrated circuit device and production thereof
US5886876A (en) * 1995-12-13 1999-03-23 Oki Electric Industry Co., Ltd. Surface-mounted semiconductor package and its manufacturing method
JPH09232721A (en) * 1996-02-28 1997-09-05 Hitachi Aic Inc Printed wiring board manufacturing method
WO2007116657A1 (en) * 2006-04-10 2007-10-18 Panasonic Corporation Relay substrate, method for manufacturing the relay substrate and three-dimensional circuit device using the relay substrate
US8159829B2 (en) 2006-04-10 2012-04-17 Panasonic Corporation Relay substrate, method for manufacturing the relay substrate and three-dimensional circuit device using the relay substrate
JP4968255B2 (en) * 2006-04-10 2012-07-04 パナソニック株式会社 Relay board, manufacturing method thereof, and three-dimensional circuit device using the same

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