JPH01134530A - Pipeline controller - Google Patents

Abstract

PURPOSE:To eliminate the disturbance of a pipeline and to realize the high-speed working of a pipeline controller by producing forcibly the arithmetic cycles which are simultaneously practicable into a relevant processing flow when an instruction requiring no arithmetic operation is included among continuous arithmetic instructions. CONSTITUTION:When the instruction to be processed is equal to an arithmetic instruction, a microcode corresponding to said instruction is stored in a 1st memory means 1. When the instruction to be processed is equal to such an instruction requiring no arithmetic operation as a load instruction, etc., a microcode corresponding to said instruction is stored in a 2nd memory means 2. In case of the arithmetic instruction, an arithmetic part 3 is started by a pipeline control part 4 based on the V-cycle (simultaneously practicable arithmetic cycles) signal received from the means 1. While the data-through signal is given to the part 3 from the part 4 based on the V-cycle forcible signal received from the means 2 in case of an instruction requiring no arithmetic operation. Thus the data-through actions are carried out at the part 3 for a single cycle.

Description

[Detailed Description of the Invention] [Summary] A pipeline processing control device used as a means of speeding up processing in an electronic computer system? JL, by forcibly providing a specific operation cycle that can be executed at the same time as a cycle other than the V cycle of the operation state of other instruction processing flows as a cycle in a load type instruction that does not originally require operation. A first storage means for recording control data 1, 9 when the instruction to be processed is an arithmetic instruction, and the instruction to be processed is an instruction that does not require an arithmetic operation, with the aim of realizing high-speed processing. a second storage means that sometimes stores control data; a calculation section that executes an operation; and an output from the first storage means when the operation instruction is executed, causing the calculation section to execute the specific operation cycle (V). let me,
Further, the present invention is configured to include a pipeline control section that forcibly generates the above-mentioned cycle (2) using the output from the second storage means when executing the instruction that does not require an operation.

[Industrial application field]

The present invention relates to a pipeline processing control device used to increase processing speed in an electronic computer system.
In particular, during load-type instructions that do not originally require calculations, the operation stages of other instruction processing flows are processed as ■cycles.
The present invention relates to a pipeline processing control method that enables further speeding up of processing by forcibly providing an arithmetic cycle that can be executed simultaneously with other cycles.

[Conventional technology]

Pipeline processing is widely used to speed up the processing of electronic computers. This divides the execution procedure of a given instruction into each stage of operation, such as instruction decoding, address calculation, operand fetching, operation, and result storage, and prepares a hardware mechanism to execute each stage. After the stage operation is completed, the execution section of each stage passes the result to the next stage execution section and executes the same stage for the next instruction. At a certain point in time, an apparent number of instructions are processed simultaneously and in parallel, improving the overall processing speed.

On the other hand, the machine cycle of a computer is determined by the model,
Whether or not each stage of instruction decoding, address calculation, etc. described above is all executed in one machine cycle has a large effect on the speed of pipeline processing. If all stages finish in one cycle, there will be no pipeline disturbance,
Although processing can be performed in the shortest possible time, in reality there are few stages that require more than two machine cycles.

A typical example is the arithmetic execution stage in an arithmetic instruction. Execution of an operation may require several cycles depending on its content.

As a means of eliminating pipeline turbulence and speeding up the execution of arithmetic instructions, it is possible to execute a specific cycle among the multiple cycles that make up the arithmetic stage at the same time as cycles other than this specific cycle in the arithmetic stage of other instructions. There is a way to do this. This simultaneously executable operation cycle is provided by microcode as necessary and is called a vanish cycle, and hereinafter referred to as a V cycle.

The processing speed-up when the arithmetic stages are divided as described above and arithmetic cycles that can be executed simultaneously, that is, (2) cycles are provided, will be explained using FIG. 5 as an example. The figure ta> is ■
(b) shows the case where no cycle is provided, and (b) shows the case where it is provided.

Symbols representing each stage, A.

T, B, IF, W are respectively D for instruction decoding, 8 for address calculation when reading data, T for checking whether data is in buffer storage, and 7 for execution from logical address. Conversion to address (translation)
, B is a read stage of buffer data, E is an execution stage, and W is a write stage where the result is stored in a register or the like.

In FIG. 5(a), it is assumed that instructions ■ and ■ are the same type of arithmetic instructions and have the same minimum processing time. However, the calculation stage is 2
It spans a cycle and the instruction I beam.

It is processed in 7 cycles of A, T, B, E, E, and W. Instruction ■ starts its processing one cycle later than instruction l, and after the stage operation progresses in the order of D, A, T, B, originally it should immediately move to the next E stage, but Since the E stage of instruction I continues, it is not possible to move to the E stage, and it is necessary to repeat the B stage again and wait.

As a result, processing of instruction H requires eight cycles, resulting in a processing delay.

On the other hand, in Figure 5 (bl), the calculation stage 2 cycle is divided into E and ■ cycles, and in order to make the ■ cycles executable at the same time, the instruction It is possible to start executing the stage, there is no need to wait at the B stage, and the instruction
End with a cycle.

[Problem that the invention seeks to solve]

As described above, by providing arithmetic cycles that can be executed simultaneously in arithmetic instructions, that is, V cycles, it is effective to speed up processing when the arithmetic instructions are consecutive. However, if a register is used in the middle of an operation, it is necessary to use a load type instruction to write data to the register.

This load type instruction is generally processed in one cycle and does not require an arithmetic stage, so there is a problem that the above-mentioned cycle cannot be generated, resulting in a disturbance in the vibe line and hindering speedup. . An example of this will be explained with reference to FIG.

In FIG. 6, the operation stage for operation instruction I extends over two cycles of E and V. In the next load instruction, D, A, T,
There are no problems with the processing of each stage up to B. The subsequent execution stage, load execution stage E, is the V of instruction I.
Although it is possible to execute in the section where the cycle is being executed,
The section of the next W stage overlaps with the W stage of the operation instruction (2). So I waited at stage B, then D, A.
.

Load instructions are processed in the order of T, [3, B, E, and W. Here, it is not possible to wait at E like DSA, TSBSE, E, and W. The reason for this is that when E9E and E operations are continued, the E operation is terminated by the processing end signal from the arithmetic unit, and the arithmetic unit is not activated by load instructions and no processing end signal is generated.
This is because the end point of the E operation is not specified.

Repetition of the B stage in a load instruction causes a delay in processing subsequent arithmetic instructions. In other words, after the next operation instruction ■ processes each stage A and T in one cycle, it is not possible to immediately move to the B stage and it is necessary to wait at the T stage. You will be required to wait on stage.

In view of the above-mentioned problems, the present invention provides a pipeline processing control device that realizes further speed-up of processing by providing an arithmetic cycle that can be forcibly executed simultaneously during load instructions, that is, a cycle. With the goal.

[Means for Solving the Problems] A block diagram of the principle of the present invention is shown in FIG. In the figure, the first storage means 1 stores control data in control memory when the instruction to be processed is an operation instruction, and the second storage means 2 stores control data when the instruction to be processed is an operation instruction, and the second storage means 2 stores control data when the instruction does not require operation, such as a load instruction. It is used to store control data when . When the instruction is an arithmetic instruction, the pipeline control section 4 causes the arithmetic section 3 to execute simultaneously executable arithmetic cycles, that is, V cycles, based on the output from the first memory 121, and when the instruction does not require an arithmetic operation, This is for forcibly generating only one (2) cycle while keeping the arithmetic unit 3 in a data-through state.

[For production]

When the instruction to be processed in FIG. 1 is an arithmetic instruction, for example, the control storage (C3
)) is stored in a first storage means, for example, a data register (A)1. On the other hand, if the instruction is a load type, the control data is stored in a second storage means, such as a data register (B
)2. The two registers are selected, for example, by selecting register (A) when a specific bit of the microcode is 1°, and selecting register (B) when another specific bit is 1°.

In response to an arithmetic instruction, the vibe line control section 4 outputs an activation signal to the arithmetic section 3 in response to a V cycle signal from the first storage means 1, for example, the data register (A), thereby activating the arithmetic section. When the calculation is completed, the calculation unit 3 outputs a processing end signal to the pipeline control unit 4, and the cycle operation ends.

On the other hand, when the instruction is a load type,
The pipeline control section 4 outputs a data through signal to the calculation section 3 in response to a V cycle forcing signal from the second storage means 2, for example, the data register (B). At this time, the arithmetic unit 3 is not activated for the (2) cycle, and is maintained in a data-through state for data input/output to a register (not shown).

The pipeline control unit 4 forcibly generates the (1) cycle and completes it in only one cycle.

As described above, in the present invention, for the purpose of preventing pipeline disturbances, an operation cycle that can be executed simultaneously, that is, a (2) cycle, is forcibly generated during an instruction that does not require an operation.

〔Example〕

FIG. 2 shows an overall block diagram of an embodiment of the pipeline processing control device of the present invention. In the figure, data register (A) 1 is used to store control data in control memory when the instruction to be processed is an operation instruction, and data register (B) 2 is used to store control data when the instruction to be processed is an instruction that does not require operation. . The arithmetic unit (E unit) 3 is a part of an arithmetic stage consisting of a plurality of machine cycles, and is capable of executing an arithmetic cycle that can be executed simultaneously with other parts, that is, a cycle operation.

The pipeline control unit 4 controls pipeline processing of instructions. The control memory (CS) 5 stores a plurality of microcodes for control, and the storage address of each microcode has a one-to-one correspondence with the operation code (OP-CODE) of the instruction given to the control memory 5. specified. The register group 6 stores the operation results in the middle of the operation to the operation unit 3.
The buffer control section (S unit) 7 controls the buffer in order to store the calculation results in the external memory 8 and to take in data from the external memory 8.

In the present invention, during the flow of pipeline processing of instructions that do not require arithmetic operations, control data is used to forcibly generate only one arithmetic cycle that can be executed simultaneously, that is, one cycle. is conceptually shown in Figure 3.

In the figure, the storage address of the microcode in the control memory 5 is specified corresponding to the operation code, and the microcode at that address, in the figure, the microcode ■
is read out. The microcode ■ is composed of, for example, 10 bits, of which one particular bit, column A, is a bit that sets "1" when the instruction is an arithmetic instruction and control data is stored in data register (A) 1. , Another specific 1 bit, B 1, is an instruction that does not require any calculation, and is set to “1” when storing control data in data register (B) 2.
This is the bit that makes you stand out. The other 8 bits store control data for controlling the buffer control section (S unit) 7, arithmetic section (E unit) 3, etc. After these data are stored in either of the two data registers 1.2, they are output as control signals for each section.

The operation of the embodiment of the present invention will be explained using FIGS. 2 and 3. In FIG. 2, the operation code of the instruction is given, an address in the control storage (CS) 5 is specified, and the microcode at that address is read out. The code is designated as microcode ■ in Figure 3. If there is a specific bit in the microcode ■, "1°" in the A column, it is an arithmetic instruction, so the control data is stored in the data register (A).
1 cent. The data register (A) 1 notifies the pipeline control unit 4 that it is the (2) cycle of the operation stage as a (2) cycle signal, and the pipeline control unit 4 issues an activation signal to the operation unit 3. Arithmetic unit 3
When it receives the activation signal, it takes out the operation data from the register group 6 or the buffer control section 7, performs the operation, and returns the result to the register group 6 or the buffer control section 7, and at the same time sends the operation data to the pipeline control section. A processing end signal is output to 4.

Another specific bit of the microcode in Figure 3 is “1” in the B grip.
If it is, for example, it is a load type instruction, and the control data is sent to the data register (B) 2. A signal is sent from the data register (B) 2 to the pipeline control unit 4 to forcibly generate the cycle, and the pipeline control unit 4 does not issue a start signal to the calculation unit 3. Generate a V cycle and finish it in only one cycle. That is, if it is a load-related instruction, the pipeline control unit 4 outputs a data through signal to the calculation unit 3, and the calculation unit 3 outputs a data through signal to the buffer control unit 7, for example.
A data through operation is performed in which the data from the register is sent as is to the register group 6. The calculation unit 3 does not output a processing end signal,
(2) Cycle termination is controlled by the pipeline control section 4.

As described in detail above, FIG. 4 shows an example of pipeline processing when a V cycle is forcibly generated during an instruction that does not require an operation, such as a load instruction. In the figure, the processing of the load instruction starts one cycle later than the operation instruction I, but the load execution stage, that is, E
A V cycle, which is an arithmetic cycle that can be executed simultaneously, is forcibly provided immediately after the stage. As a result, the next operation instruction ■ does not need to wait in the T stage compared to the case where no V cycle is provided during the load instruction as shown in FIG. Processing is one cycle faster than in the case shown in the figure. Similarly, the operation instruction (2) is also executed in 7 cycles, which speeds up the processing by 1 cycle.

In this embodiment, a V cycle is forcibly generated when a specific bit in the microcode in the control memory 5 shown in FIG. Of course, it is also possible to perform forced cycle generation.

〔Effect of the invention〕

In a computer system that processes instructions in a pipeline method, when an instruction that does not require an operation such as a load instruction is interposed between consecutive operation instructions, a calculation cycle that can be executed simultaneously is forcibly generated during the processing flow. According to
This eliminates pipeline turbulence and increases speed.

[Brief explanation of the drawing]

Figure 1 is a principle block diagram of the pipeline processing control device of the present invention, Figure 2 is an overall block diagram of an embodiment of the present invention, and Figure 3 is
Conceptual diagram of control memory for cycle generation. Figure 4 is an explanatory diagram of pipeline processing when a ■ cycle is generated during a load instruction. Figure 5 (a), (bl is a ■ cycle only during an operation instruction. Pipeline processing explanatory diagram in a conventional example where
The figure is an explanatory diagram of processing delay when there is a load instruction between consecutive operation instructions. 1... Data register (A), 2... Data register (B), 3... Arithmetic unit (E unit), 4... Pipeline control unit, 5... Control memory (CS) , 6... Register group, 7... Buffer control section (S unit), 8... External memory. 07
Figure 7Figure 2

Claims (1)

[Claims] 1) When processing an arithmetic instruction, a certain arithmetic cycle (V) in an arithmetic execution stage consisting of a plurality of machine cycles,
Cycles (E) other than the cycle (V) corresponding to the specific operation cycle (V) in the operation execution stage of other operation instructions
), a first storage means (1) stores control data when the instruction to be processed is an arithmetic instruction; a second storage means (2) for storing control data when the command is an instruction; a calculation section (3) for performing calculations; The arithmetic unit (3) executes the specific arithmetic cycle (V) of the arithmetic instruction execution stage, and the specific arithmetic cycle (V) is executed by the output from the second storage means (2) when the instruction that does not require the arithmetic operation is executed. A pipeline control device comprising a pipeline control unit (4) that forcibly generates a specific operation cycle (V) corresponding to (V). 2) The pipeline control device according to claim 1, wherein the instruction that does not require arithmetic operations is a load instruction. 3) The pipeline control device according to claim 1, wherein the arithmetic execution stage of the arithmetic instruction is two cycles. 4) The pipeline control device according to claim 3, wherein the instruction execution stage of the instruction that does not require arithmetic operations is one cycle.