JPH01132169A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01132169A JPH01132169A JP29136987A JP29136987A JPH01132169A JP H01132169 A JPH01132169 A JP H01132169A JP 29136987 A JP29136987 A JP 29136987A JP 29136987 A JP29136987 A JP 29136987A JP H01132169 A JPH01132169 A JP H01132169A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- gate electrode
- gate
- semiconductor device
- diffused
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 239000012535 impurity Substances 0.000 claims abstract description 25
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims abstract description 14
- 229910052698 phosphorus Inorganic materials 0.000 claims abstract description 14
- 239000011574 phosphorus Substances 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 17
- 230000015556 catabolic process Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- 238000009413 insulation Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
Landscapes
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明は、半導体装置に関し、特に浮遊ゲート構造を有
する半導体装置のゲート電極の構造に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to the structure of a gate electrode of a semiconductor device having a floating gate structure.
［従来の技術］
従来、この種の半導体装置として浮遊ゲートを有する不
揮発性ＭＯ８（Ｍｅｔａｌ ＯｘｉｄｅＳｅｍｉｃｏ
ｎｄｕｃｔｏｒ）メモリがある。[Prior Art] Conventionally, this type of semiconductor device is a non-volatile MO8 (Metal Oxide Semiconductor) having a floating gate.
(inductor) memory.
以下には、この不揮発性ＭＯＳメモリのゲート電極の構
造を第２Ａ図および第２Ｂ図を用いて製造工程順に説明
する。The structure of the gate electrode of this nonvolatile MOS memory will be explained below in the order of manufacturing steps with reference to FIGS. 2A and 2B.
第２Ａ図に示すように、シリコン基板１の一生面上にフ
ィールド酸化膜２、第１ゲート酸化膜３を形成した後、
第１ゲート電極となる多結晶シリコン膜４を約４０００
人の厚さに堆積する。次に、多結晶シリコン膜４に比較
的低濃度たとえば４Ｘ１０２０ｃｍ−２でｎ型不純物を
拡散した後、写真製版技術を用いて多結晶シリコン膜４
をＣＦ、ガスなどにより異方性プラズマエツチングして
第１ゲート電極４を形成する。As shown in FIG. 2A, after forming a field oxide film 2 and a first gate oxide film 3 on the entire surface of the silicon substrate 1,
The polycrystalline silicon film 4, which will become the first gate electrode, has a thickness of about 4,000 mm.
Deposits to the thickness of a person. Next, after diffusing n-type impurities into the polycrystalline silicon film 4 at a relatively low concentration, for example, 4 x 1020 cm-2, the polycrystalline silicon film 4 is
The first gate electrode 4 is formed by anisotropic plasma etching using CF, gas, or the like.
次に第２Ｂ図に示すように、多結晶シリコンの第１ゲー
ト電極４を熱酸化処理し厚さ６００Ａ程度の第２ゲート
酸化膜５を形成する。これにより第１ゲート電極４はそ
の周囲を酸化膜に囲まれた浮遊ゲートを構成する。そし
て、その上に第２ゲート電極となる多結晶シリコン膜６
を化学的気相成長法により厚さ３０００Ａ程度堆積する
。以上の工程により第１と第２のゲート電極を有する不
揮発性メモリが製造される。Next, as shown in FIG. 2B, the first gate electrode 4 made of polycrystalline silicon is thermally oxidized to form a second gate oxide film 5 having a thickness of about 600 Å. As a result, the first gate electrode 4 constitutes a floating gate surrounded by an oxide film. Then, a polycrystalline silicon film 6 that becomes a second gate electrode is placed on top of the polycrystalline silicon film 6.
is deposited to a thickness of about 3000 Å by chemical vapor deposition. Through the above steps, a nonvolatile memory having first and second gate electrodes is manufactured.
［発明が解決しようとする問題点コ
上記のように、従来の浮遊ゲート型不揮発性ＭＯＳメモ
リは、１層の浮遊ゲート電極で形成されている。そして
、この浮遊ゲート電極である第１ゲート電極４の絶縁耐
圧は、この第１ゲート電極４に拡散されるリンなどのｎ
型不純物の濃度に依存する。すなわち、第１ゲート電極
４のリン濃度が高ければ、第２ゲート電極６に対する絶
縁耐圧 □は向上する。しかし、一方で第１ゲート電極
４を熱酸化処理を行なって第２ゲート酸化膜５を形成す
る工程では、第１ゲート？ＩＳ極４中に拡散されたリン
が再拡散し第１ゲート酸化膜２を劣化させるなどの悪影
響が生じる。したがって、この場合にはリン濃度が低い
方が好ましい。[Problems to be Solved by the Invention] As described above, the conventional floating gate nonvolatile MOS memory is formed of a single layer of floating gate electrodes. The dielectric breakdown voltage of the first gate electrode 4, which is this floating gate electrode, is
Depends on the concentration of type impurities. That is, if the phosphorus concentration of the first gate electrode 4 is high, the dielectric strength voltage □ with respect to the second gate electrode 6 is improved. However, on the other hand, in the process of thermally oxidizing the first gate electrode 4 to form the second gate oxide film 5, the first gate electrode 4 may be thermally oxidized. The phosphorus diffused into the IS pole 4 is re-diffused, causing adverse effects such as deterioration of the first gate oxide film 2. Therefore, in this case, it is preferable that the phosphorus concentration is low.
したがって、第１ゲート電極４ではｌ５ｔｆｆｉ内での
リン濃度は第２ゲート電極６側と基板１側とで異なる濃
度分布を有することが最適であるが、従来の１層の第１
ゲート電極の構造ではこれを実現することができなかっ
た。Therefore, in the first gate electrode 4, it is optimal that the phosphorus concentration within l5tffi has different concentration distributions on the second gate electrode 6 side and the substrate 1 side.
This could not be achieved with the structure of the gate electrode.
したがって、本発明は、第１ゲート電極をその間に極め
て薄い酸化膜を介して２層に分離し、かつその上層電極
と下層電極とをそれぞれ最適な不純物濃度に設定するこ
とにより絶縁耐圧が高い電極を有した半導体装置を提供
することを目的とする。Therefore, the present invention provides an electrode with high dielectric strength by separating the first gate electrode into two layers with an extremely thin oxide film between them, and setting the upper layer electrode and the lower layer electrode to optimal impurity concentrations. An object of the present invention is to provide a semiconductor device having the following characteristics.
［問題点を解決するための手段］
本発明による半導体装置は、絶縁膜中に設けられた浮遊
ゲートである第１のゲート電極と、前記第１のゲート電
極の上に前記絶縁膜を介して設けられた制御ゲートであ
る第２のゲート電極とを備えた半導体装置であり、前記
第１のゲート電極は絶縁膜を介して分離して積層した２
層の電極を備え、前記２層の電極のうち、前記第２のゲ
ート電極側に位置する一方の電極は相対的に不純物濃度
が高くなるように不純物が拡散され、他方の電極は相対
的に不純物濃度が低くなるように不純物が拡散されてい
ることを特徴としている。[Means for Solving the Problems] A semiconductor device according to the present invention includes a first gate electrode, which is a floating gate provided in an insulating film, and a gate electrode formed on the first gate electrode through the insulating film. The semiconductor device includes a second gate electrode which is a control gate provided, and the first gate electrode is a two-layered semiconductor device separated by an insulating film.
impurity is diffused in one electrode located on the second gate electrode side among the two layer electrodes so that the impurity concentration is relatively high, and the other electrode is provided with a relatively high impurity concentration. It is characterized in that impurities are diffused so that the impurity concentration is low.
［作用］
本発明における半導体装置は、浮遊ゲート電極を薄い酸
化膜を介して２層に分離している。そして、上層電極は
リンなどの不純物濃度を高く設定することにより、第２
ゲート電極に対する絶縁耐圧を高くすることができる。[Function] In the semiconductor device of the present invention, the floating gate electrode is separated into two layers via a thin oxide film. Then, by setting the upper layer electrode to a high concentration of impurities such as phosphorus,
The dielectric strength voltage for the gate electrode can be increased.
また、下層電極では、リンなどの不純物濃度を低く設定
することにより製造工程で行なわれる熱処理によって第
１ゲート酸化膜の劣化が生じないようにしている。Further, in the lower electrode, the concentration of impurities such as phosphorus is set low to prevent the first gate oxide film from deteriorating due to heat treatment performed in the manufacturing process.
［実施例］ 以下、本発明の一実施例を図を用いて説明する。[Example] An embodiment of the present invention will be described below with reference to the drawings.
第１Ａ図および第１Ｂ図は本発明による浮遊ゲート型不
揮発性ＭＯＳメモリのゲート電極をその製造工程に従っ
て示した断面図である。1A and 1B are cross-sectional views showing a gate electrode of a floating gate nonvolatile MOS memory according to the present invention according to its manufacturing process.
第１Ａ図に示すように、シリコン基板１の一生面上に、
フィールド酸化膜２および第１ゲート酸化膜３を形成す
る。さらに、多結晶シリコン７を化学気相成長法により
約１８００Ａ厚さに形成した後、写真製版技術を用いて
多結晶シリコン膜７をＣＦ４ガスにより異方性プラズマ
エツチングする。次に、多結晶シリコン膜７にリンなど
のｎ型不純物を不純物濃度２×１０２°ｃｒ！１−”で
拡散し、下層第１ゲート電極７を形成する。次いで、多
結晶シリコンの下層第１ゲート電極７を熱酸化処理する
ことにより膜厚が約１００人の酸化膜８を形成する。さ
らにその上に、多結晶シリコン膜９を化学的気相成長法
により膜厚的１８００Ａに形成した後、写真製版技術を
用いて多結晶シリコン膜９をＣＦ４ガスにより異方性プ
ラぞマエッチングする。そして、この多結晶シリコン膜
９にリンなどのｎ型不純物を不純物濃度６Ｘ１０２６ｃ
ｍ−”で拡散し、上層第１ゲート専極９を形成する。As shown in FIG. 1A, on the whole surface of the silicon substrate 1,
A field oxide film 2 and a first gate oxide film 3 are formed. Furthermore, after forming polycrystalline silicon 7 to a thickness of about 1800 Å by chemical vapor deposition, polycrystalline silicon film 7 is anisotropically plasma etched with CF4 gas using photolithography. Next, an n-type impurity such as phosphorus is added to the polycrystalline silicon film 7 at an impurity concentration of 2×102°cr! 1-'' to form a lower first gate electrode 7. Next, the lower first gate electrode 7 made of polycrystalline silicon is thermally oxidized to form an oxide film 8 having a thickness of about 100 mm. Further, a polycrystalline silicon film 9 is formed thereon to a thickness of 1800 Å by chemical vapor deposition, and then the polycrystalline silicon film 9 is anisotropically plasma etched with CF4 gas using photolithography. Then, an n-type impurity such as phosphorus is added to this polycrystalline silicon film 9 at an impurity concentration of 6×1026c.
m-'' to form the upper layer first gate exclusive pole 9.
次いで、第１Ｂ図に示すように、多結晶シリコンの上層
第１ゲート電極９を熱酸化処理し膜厚的６０ＯＡの第２
ゲート酸化膜５を形成する。そして、その上に多結晶シ
リコン膜６を約３０００Ａ厚さに化学気相成長法により
堆積し、第２ゲート電極６を形成する。Next, as shown in FIG. 1B, the upper layer first gate electrode 9 of polycrystalline silicon is thermally oxidized to form a second gate electrode 9 with a film thickness of 60 OA.
A gate oxide film 5 is formed. Then, a polycrystalline silicon film 6 is deposited thereon to a thickness of about 3000 Å by chemical vapor deposition to form the second gate electrode 6.
以上のように構成した場合、第１ゲート電極は酸化膜８
を介して２層に分離され、その上層電極９と下層電極７
ではそれぞれ異なったリン濃度にすることができる。す
なわち、上層電極に対しては高濃度のリンを拡散し、ま
た下層電極に対しては低濃度のリンを拡散することによ
り絶縁耐圧が高い電極を有する不遊ゲート型不揮発性Ｍ
ＯＳメモリが製造される。In the case of the above structure, the first gate electrode is formed by the oxide film 8.
The upper layer electrode 9 and the lower layer electrode 7 are separated into two layers through the
In this case, different phosphorus concentrations can be obtained. In other words, a non-volatile gate-type non-volatile M having an electrode with high dielectric strength by diffusing high concentration phosphorus into the upper layer electrode and diffusing low concentration phosphorus into the lower layer electrode.
OS memory is manufactured.
［発明の効果］
以上のように、本発明によれば浮遊ゲート電極構造を有
する半導体装置の第１ゲート電極が、酸化膜を介して２
層に分離された構造としたのでその上層部と下層部で各
々不純物濃度を調整することによって、浮遊ゲート電極
の絶縁耐圧を高くすることができ、特性の優れた半導体
装置を得ることができる。[Effects of the Invention] As described above, according to the present invention, the first gate electrode of the semiconductor device having the floating gate electrode structure is connected to the second gate electrode through the oxide film.
Since the structure is separated into layers, by adjusting the impurity concentration in each of the upper and lower layers, the dielectric breakdown voltage of the floating gate electrode can be increased, and a semiconductor device with excellent characteristics can be obtained.
第１Ａ図および第１Ｂ図は、本発明の実施例の半導体装
置の製造工程を示す断面図である。
第２Ａ図および第２Ｂ図は、従来の半導体装置の製造工
程を示す断面図である。
図において、３は第１ゲート酸化膜、５は第２ゲート酸
化膜、６は第２ゲート電極、７は下層第１ゲート電極、
８は酸化膜、９は上層第１ゲート電極を示す。
なお、図中同一符号は同一または相当する部分を示す。1A and 1B are cross-sectional views showing the manufacturing process of a semiconductor device according to an embodiment of the present invention. FIGS. 2A and 2B are cross-sectional views showing the manufacturing process of a conventional semiconductor device. In the figure, 3 is a first gate oxide film, 5 is a second gate oxide film, 6 is a second gate electrode, 7 is a lower first gate electrode,
Reference numeral 8 indicates an oxide film, and reference numeral 9 indicates an upper layer first gate electrode. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (2)
ート電極と、前記第１のゲート電極の上に前記絶縁膜を
介して設けられた制御ゲートである第２のゲート電極と
を備えた半導体装置において、前記第１のゲート電極は
絶縁膜を介して分離して積層した２層の電極を備えてお
り、 前記２層の電極のうち、前記第２のゲート電極側に位置
する一方の電極は、相対的に不純物濃度が高くなるよう
に不純物が拡散され、他方の電極は相対的に不純物濃度
が低くなるように不純物が拡散されていることを特徴と
する、半導体装置。(1) A first gate electrode, which is a floating gate provided in an insulating film, and a second gate electrode, which is a control gate, provided on the first gate electrode via the insulating film. In the semiconductor device, the first gate electrode includes two layers of electrodes separated and laminated via an insulating film, and of the two layers of electrodes, the first gate electrode is located on the side of the second gate electrode. A semiconductor device characterized in that impurities are diffused in one electrode so that the impurity concentration is relatively high, and impurities are diffused in the other electrode so that the impurity concentration is relatively low.
ある特許請求の範囲第１項記載の半導体装置。(2) The semiconductor device according to claim 1, wherein the impurity diffused into the two-layer electrode is phosphorus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62291369A JP2603088B2 (en) | 1987-11-17 | 1987-11-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62291369A JP2603088B2 (en) | 1987-11-17 | 1987-11-17 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01132169A true JPH01132169A (en) | 1989-05-24 |
| JP2603088B2 JP2603088B2 (en) | 1997-04-23 |
Family
ID=17768025
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62291369A Expired - Lifetime JP2603088B2 (en) | 1987-11-17 | 1987-11-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2603088B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5229631A (en) * | 1990-08-15 | 1993-07-20 | Intel Corporation | Erase performance improvement via dual floating gate processing |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6010679A (en) * | 1983-06-29 | 1985-01-19 | Mitsubishi Electric Corp | Semiconductor memory |
| JPS61255071A (en) * | 1985-05-07 | 1986-11-12 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPS61294870A (en) * | 1985-06-21 | 1986-12-25 | Nec Corp | Non-volatile semiconductor memory device |
-
1987
- 1987-11-17 JP JP62291369A patent/JP2603088B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6010679A (en) * | 1983-06-29 | 1985-01-19 | Mitsubishi Electric Corp | Semiconductor memory |
| JPS61255071A (en) * | 1985-05-07 | 1986-11-12 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPS61294870A (en) * | 1985-06-21 | 1986-12-25 | Nec Corp | Non-volatile semiconductor memory device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5229631A (en) * | 1990-08-15 | 1993-07-20 | Intel Corporation | Erase performance improvement via dual floating gate processing |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2603088B2 (en) | 1997-04-23 |
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