JPH01130587A - Integrated circuit - Google Patents
Integrated circuitInfo
- Publication number
- JPH01130587A JPH01130587A JP62290255A JP29025587A JPH01130587A JP H01130587 A JPH01130587 A JP H01130587A JP 62290255 A JP62290255 A JP 62290255A JP 29025587 A JP29025587 A JP 29025587A JP H01130587 A JPH01130587 A JP H01130587A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- ceramic
- dielectric
- integrated circuit
- superconducting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 239000000919 ceramic Substances 0.000 claims abstract description 29
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 238000000034 method Methods 0.000 abstract description 4
- 230000000149 penetrating effect Effects 0.000 abstract description 4
- 230000001747 exhibiting effect Effects 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 28
- 238000005516 engineering process Methods 0.000 description 3
- 238000010276 construction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 229910000831 Steel Inorganic materials 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052746 lanthanum Inorganic materials 0.000 description 1
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum atom Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は低損失で簡易な多層構造の集積回路に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an integrated circuit having a low loss and simple multilayer structure.
第３図は１例えば実開昭６１−０５７６０５号公報に示
され友従来のこの種の集積回路を示す構成斜視−１第４
図は上記集積回路の分解斜視図である。FIG. 3 is a perspective view of a conventional integrated circuit of this kind as shown in, for example, Japanese Utility Model Application Publication No. 61-057605.
The figure is an exploded perspective view of the integrated circuit.
図において、（１１は第１の誘電体基板、（２）は第２
の誘電体基板、（３）ＩＩｉＩ２Ｏ３電体基板ハ２１を
貫通する孔を通じて設けられ次貫通導体、（４）ハ第１
の表面金媚膜、【５）は第１の裏面金属膜１６）＃−ｊ
第２の表面金Ｊｉ［、（７）ｄ第２の裏面金属膜、（８
）は接地用金属板である。In the figure, (11 is the first dielectric substrate, (2) is the second
a dielectric substrate, (3) a second through conductor provided through a hole penetrating the IIIiI2O3 electric substrate C, and (4) a first through conductor.
[5] is the first back metal film 16) #-j
Second surface gold Ji [, (7) d second back metal film, (8
) is a grounding metal plate.
貫通導体＋３）は第２の表面金属膜（６）と第２の裏面
金属膜（１）とを導通式せる九めのものである。The through conductor +3) is the ninth one that connects the second front metal film (6) and the second back metal film (1).
第１の裏面金属膜［５）と第２の表面金属膜（６）とは
半田付は等によ多接続されている。The first back metal film [5] and the second front metal film (6) are connected by soldering or the like.
例えば、第３図の集積回路では、第１の表面金属膜（４
）と第１の裏面金属膜１５）と！マイクロストリップＷ
Ｉ＆路が構成され、第２の表面金属膜（６）にてスロッ
ト線路が構成されてｉる。すなわち、第１の誘電体基板
キ１）、第２の誘電体基板（２）の面上に設けた導体膜
にてそれぞれ回路が構成され、かつ、！Ｉ誘電体基板表
裏を必要に応じて導通ずる友めに貫通導体が用いられて
いる。For example, in the integrated circuit of FIG. 3, the first surface metal film (4
) and the first back metal film 15)! Microstrip W
An I& path is formed, and a slot line is formed with the second surface metal film (6). That is, a circuit is formed by the conductor films provided on the surfaces of the first dielectric substrate (1) and the second dielectric substrate (2), and! A through conductor is used to connect the front and back sides of the dielectric substrate as necessary.
従来のこの種の集積回路では貫通導体を形成するｔめ、
誘電体基板に貫通孔ｆ：設け、上記貫通孔を薄膜または
厚膜技術にニジ金属で被覆している。In conventional integrated circuits of this type, through-conductors are formed;
A through hole f is provided in the dielectric substrate, and the through hole is covered with a rainbow metal using thin film or thick film technology.
まｆｃ、誘電体基板の面上の金属膜も薄膜ま九は厚膜技
術によって形成さ几る。更に、上記、各誘電体基板を多
層に配置する定め、半田付は等が必要である。However, the metal film on the surface of the dielectric substrate is also formed by thick film technology. Furthermore, as mentioned above, it is necessary to arrange the dielectric substrates in multiple layers, solder them, etc.
従来のこの種の集′槓回絡でｌま、貫通導体および各誘
電体基板の面上に設ける導体膜に金属を用−るのでその
導体損により、回路損失が大きいという問題点があり、
ま九、構造お工び形成方法も複雑であるという問題点か
あつ九。In conventional integrated circuits of this type, metal is used for the through conductor and the conductor film provided on the surface of each dielectric substrate, so there is a problem that the circuit loss is large due to the conductor loss.
Another problem is that the method for forming the structure is complicated.
この発明は上記のような問題点を解消するｔめになされ
友もので、低損失で簡易な多層構造の集積回路を得るこ
とｔ目的とする。The present invention has been made to solve the above-mentioned problems, and an object thereof is to obtain an integrated circuit having a low loss and simple multilayer structure.
この発明に係る集積回路は多層に配置された各誘電体基
板の上面および下面ｒ電気的に導通ずる友めの貫通導体
を超電導セラミックで構成するとともに、各誘電体基板
の面上に設ける導体膜を超電導セラミックにより構成し
ｔものである。In the integrated circuit according to the present invention, the upper and lower surfaces of each dielectric substrate arranged in multiple layers are made of superconducting ceramic through-hole conductors that are electrically conductive, and a conductor film is provided on the surface of each dielectric substrate. is made of superconducting ceramic.
この発明に２ける集積回路は貫通導体および導体ｄｌｌ
超電導セラミックで構成しているので、低損失で、かつ
構成も簡易である。The integrated circuit according to the second aspect of the present invention includes a through conductor and a conductor dll.
Since it is made of superconducting ceramic, it has low loss and is simple in construction.
以下、この発明の一実施例を図について説明する。第１
図にお＾て、叫は誘電体である第１のセラミック基板、
（ロ）は１ＪＩＪ２のセラミック基板、＠は所定温度で
鍋温超電導を発揮する超゛ｔ４−ｔニアビックで構成さ
れ次貫通導体、Ｑ３は上記超電導セラミックで構成され
次導体膜である。An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, the first ceramic substrate, which is a dielectric,
(B) is a 1JIJ2 ceramic substrate, @ is a secondary through conductor made of super t4-t near conductor which exhibits hotpot superconductivity at a predetermined temperature, and Q3 is a secondary conductor film made of the above-mentioned superconducting ceramic.
な２、旨温で超゛４導を呈する超電導セラミック基シて
は例えばランタン（Ｌａ）−バ’） ７ Ａ （Ｂａ）
−鋼（Ｃｕ）−酸素（０）系やイントリワム（Ｙ）
−ｄａ −Ｃｕ−０系のものが知られている。2. A superconducting ceramic substrate exhibiting superconductivity at a certain temperature is, for example, lanthanum (La)-7A (Ba).
-Steel (Cu) -Oxygen (0) type and Intriwam (Y)
-da-Cu-0 series are known.
超電導セラミック部分は、＠移温度Ｔｃ以下で超電導状
態となシ、抵抗がほとんどゼロの導体として動作する。The superconducting ceramic portion is in a superconducting state below the transition temperature Tc and operates as a conductor with almost zero resistance.
従って、貫通導体ｆ導体膜を上記超電導セラミックを用
いて構成することにより％集積回路における損失の主要
因である導体損がほとんど無い集積回路を得ることが可
能である。Therefore, by constructing the through-conductor f conductor film using the above-mentioned superconducting ceramic, it is possible to obtain an integrated circuit with almost no conductor loss, which is the main cause of loss in integrated circuits.
また、すべてがセラミックにて構成されているので、誘
電体としてのセラミック基板と貫通導体や導体膜を形成
する九めの超電導電ラミンクｆ同時に一体焼成すること
も可能となｐ１構成および形成方法も簡易となる。In addition, since everything is made of ceramic, it is possible to simultaneously fire the ceramic substrate as a dielectric and the ninth superconducting laminated film that forms through conductors and conductive films. It becomes simple.
第２図はこの発明の他の実施例を示す斜視図で。FIG. 2 is a perspective view showing another embodiment of the invention.
図ｔｃｙいて、α４は半導体素子であるトランジスタで
ある。ま７ｔ１（ト）は金属膜である。金属膜（至）に
よって、トランジスタ（ロ）の電極と超電導セラミック
で成る導体膜（至）や貫通導体＠とをボンディングや半
田付は等により接続することかり能となる。このように
−この発明は半導体等の他の回路構成要素および金属膜
と組合わせて使用しても良い。In the figure, α4 is a transistor which is a semiconductor element. 7t1 (g) is a metal film. The electrode of the transistor (b) can be connected to the conductor film (to) or through conductor made of superconducting ceramic by bonding, soldering, etc. using the metal film (to). Thus - the invention may be used in combination with other circuit components such as semiconductors and metal films.
なお、上記実施例では、誘電体基板を２層とする場合に
ついて示したが、何層であっても良い。In the above embodiment, the dielectric substrate has two layers, but it may have any number of layers.
以上説明しｔように、この発明では複数枚の誘電体基板
をこれらの各誘電体基板の両面に導体膜があるように重
ねて配設し、上記誘電体基板のいずれかを貫通して当該
誘電体基板の両面の導体膜間７！ｅ１気的に接続する貫
通導体を有する集積回路において、上記誘電体基板をセ
ラミックで構成し、上記導体膜および貫通導体を高温−
電導セラミックで構成したので１回路損失の極めて少な
い集積回路が実現で＠１かり、基板セラミックと貫通導
体の超電導セラミックとｔ同時に一体に焼成することが
できるので、構成お工び形成方法も簡素化が可能となる
。As explained above, in the present invention, a plurality of dielectric substrates are arranged one on top of the other so that a conductive film is provided on both sides of each of the dielectric substrates, and the corresponding dielectric substrate is penetrated through any one of the dielectric substrates. Between the conductor films on both sides of the dielectric substrate 7! e1 In an integrated circuit having a through conductor that is electrically connected, the dielectric substrate is made of ceramic, and the conductor film and the through conductor are heated to a high temperature.
Since it is constructed from conductive ceramic, an integrated circuit with extremely low single-circuit loss can be achieved.The substrate ceramic and the superconducting ceramic of the through conductor can be fired simultaneously, simplifying the construction and forming method. becomes possible.
第１図はこの発明の一実施例の構成を示す斜視図、第２
図はこの発明の他の実施例の構成を示す斜視図、第３図
は従来の集積回路の構成を示す斜視５図、第４図はその
分解斜視図である。
図において、 Ｉｌｌお工び（ロ）はそれぞれ第１およ
び第２の誘電体（セラミック）基板、＠は貫通導体、Ｑ
３は導体膜、Ｑｌは金属膜である０
なお１図中同一符号は同一、ま几は相当部分を示す。FIG. 1 is a perspective view showing the configuration of an embodiment of the present invention, and FIG.
3 is a perspective view showing the structure of another embodiment of the present invention, FIG. 3 is a perspective view 5 showing the structure of a conventional integrated circuit, and FIG. 4 is an exploded perspective view thereof. In the figure, Ill work (b) is the first and second dielectric (ceramic) substrates, @ is the through conductor, and Q
3 is a conductor film, and Ql is a metal film.0 Note that the same reference numerals in Figure 1 indicate the same parts, and the marks indicate corresponding parts.
Claims (3)
面に導体膜があるように重ねて配設し、上記誘電体基板
のいずれかを貫通して当該誘電体基板の両面の導体膜間
を電気的に接続する貫通導体を有するものにおいて、 上記誘電体基板をセラミックで構成し、 上記導体膜および貫通導体を高温超電導セラミックで構
成したことを特徴とする集積回路。(1) A plurality of dielectric substrates are arranged one on top of the other so that there is a conductor film on both sides of each dielectric substrate, and the conductor on both sides of the dielectric substrate is passed through one of the dielectric substrates. An integrated circuit having a through conductor for electrically connecting films, wherein the dielectric substrate is made of ceramic, and the conductor film and the through conductor are made of high temperature superconducting ceramic.
ミックと同時に一体に焼成してなることを特徴とする特
許請求の範囲第１項記載の集積回路。(2) The integrated circuit according to claim 1, wherein the superconducting ceramic is fired simultaneously with the ceramic constituting the dielectric substrate.
設けたことを特徴とする特許請求の範囲第１項または第
２項記載の集積回路。(3) The integrated circuit according to claim 1 or 2, characterized in that a metal film is provided in a required region in contact with the superconducting ceramic.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62290255A JPH01130587A (en) | 1987-11-17 | 1987-11-17 | Integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62290255A JPH01130587A (en) | 1987-11-17 | 1987-11-17 | Integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01130587A true JPH01130587A (en) | 1989-05-23 |
Family
ID=17753767
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62290255A Pending JPH01130587A (en) | 1987-11-17 | 1987-11-17 | Integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01130587A (en) |
-
1987
- 1987-11-17 JP JP62290255A patent/JPH01130587A/en active Pending
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