JPS6122660A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6122660A
JPS6122660A JP59144728A JP14472884A JPS6122660A JP S6122660 A JPS6122660 A JP S6122660A JP 59144728 A JP59144728 A JP 59144728A JP 14472884 A JP14472884 A JP 14472884A JP S6122660 A JPS6122660 A JP S6122660A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
pad electrodes
semiconductor
base plates
electrodes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59144728A
Other languages
Japanese (ja)
Inventor
Shigeji Kinoshita
木下　繁治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59144728A priority Critical patent/JPS6122660A/en
Publication of JPS6122660A publication Critical patent/JPS6122660A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To contrive the large scale integration by a method wherein pad electrodes are provided at the inside and outside of a baseplate, and these electrodes are connected by electrical conductive parts which penetrate the base plates, and plural number of such base plates are stacked one upon another. CONSTITUTION:Pad electrodes 2a-6a are formed at the position corresponding each other of the surface and the inside of the first, the second and the third semiconductor base plates 1a-1c. The surface and the inside pad electrodes 2a, 6a, 2b, 6b, 2c, 6c are connected in the electrical conductive parts 7a-7c. When base plates 1a-1c are laminated, between pad electrodes 1a, 6a etc. are adhered and laminated by low melting solder. Since this device is stacked and solidified, the integration is possible without enlarging the plane expansion.

Description

【発明の詳細な説明】 〔発明の概要〕 この発明は半導体装置、特に半導体集積回路装置のバッ
ケージングンの高集積化を可能ならしめる構造に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Summary of the Invention] The present invention relates to a structure that enables high integration of semiconductor devices, particularly semiconductor integrated circuit devices.

〔従来技術〕[Prior art]

第１図は従来の半導体装置の構成を示す斜視図で、（１
）は半導体基板、（２）はこの半導体基板（１）の表面
に形成され外部との接続をする電極（パッド）、（３）
はチップマウント、（４）はチップマウント（３）に設
けられた外部端子、（５）はパッド電極（２）と外部端
子（４）とを接続する金属線である。FIG. 1 is a perspective view showing the configuration of a conventional semiconductor device.
) is a semiconductor substrate, (2) is an electrode (pad) formed on the surface of this semiconductor substrate (1) and connects with the outside, (3)
is a chip mount, (4) is an external terminal provided on the chip mount (3), and (5) is a metal wire connecting the pad electrode (2) and the external terminal (4).

従来の装置では上述のように単に平面的にパッケージ内
に配置されているだけであるので、装置　。In the conventional device, as mentioned above, the device is simply arranged in a two-dimensional package.

の大規模集積化をしようとすると、半導体基板内に形成
される素子の微細化を図るか、チップの大形化によるこ
とが必要である。しかし、素子の微細化は技術的限界に
近づいており、また、チップめ大形化は半導体製造プロ
セスでの歩留りの低下、またはチップの電気的特性の低
下、更にはパッケージの大形化などをもたらすという難
点があった。In order to achieve large-scale integration, it is necessary to miniaturize the elements formed within the semiconductor substrate or to increase the size of the chip. However, the miniaturization of elements is approaching its technological limit, and increasing the size of chips will lead to lower yields in the semiconductor manufacturing process, lower chip electrical characteristics, and even larger packages. There was a problem with bringing it.

〔発明の概要〕[Summary of the invention]

この発明は以上のような点に鑑みてなされたもので、半
導体基板の表裏対応位置にパッド電極を設け、表裏両パ
ッド電極間を半導体基板を貫通する導電部で接続して置
き、このような構造の半導体基板を複数枚積み重ねるこ
とによって、平面的な広がりを大きくすることなく、大
規模集積化が可能な半導体装置を提供するものである。This invention has been made in view of the above points, and it is possible to provide pad electrodes on the front and back sides of a semiconductor substrate, and connect the front and back pad electrodes with a conductive part that penetrates the semiconductor substrate. By stacking a plurality of structured semiconductor substrates, it is possible to provide a semiconductor device that can be integrated on a large scale without increasing the planar area.

〔発明の実施例〕[Embodiments of the invention]

第２図はこの発明の一実施例の構成を示す斜視図で、（
１ａ）、（ｌｂ）および（１ｃ）はそれぞれ第１．第２
および第３の半導体基板、（２ａ）および（６ａ）はそ
れぞれ第１の半導体基板（ｌａ）の表面および裏面の互
いに対応位置に形成されたパッド電極、（’？ａ）は第
１の半導体基板（１ａ）を貫通して表裏パッド電極（２
ａ）、（６ａ）を接続する導電部である。第２の半導体
基板（１ｂ）にも同様に表裏パッド電極（２１））、（
６１））および貫通接続する導電部（７ｂ）が設けられ
、第３の半導体基板（１Ｃ）にも表裏パッド電極（２ｃ
）、（ｅｃ）および貫通接続する導電部（７Ｃ）が設け
られている。FIG. 2 is a perspective view showing the configuration of an embodiment of the present invention.
1a), (lb) and (1c) respectively. Second
and a third semiconductor substrate, (2a) and (6a) are pad electrodes formed at mutually corresponding positions on the front and back surfaces of the first semiconductor substrate (la), respectively, ('?a) is the first semiconductor substrate (1a) and pass through the front and back pad electrodes (2
This is a conductive part that connects a) and (6a). The second semiconductor substrate (1b) also has front and back pad electrodes (21)), (
61)) and a conductive part (7b) that is connected through the third semiconductor substrate (1C).
), (ec) and a conductive portion (7C) which is connected through the conductive portion.

これらの構造の形成方法の一例を第１の半導体基板（１
ａ）について略説すれば、まず、第１の半導体基板（ｌ
ａ）にレーザビームなどによって貫通孔を形成し、その
後にプラズマＣｖＤ法などの薄膜形成技術によって孔の
中まで導電性皮膜で被覆し、周知の写真製版技術によっ
て表裏パッド電極（２ａ）。An example of a method for forming these structures is shown in FIG.
To briefly explain a), first, the first semiconductor substrate (l
A through hole is formed in a) using a laser beam or the like, and then the inside of the hole is coated with a conductive film using a thin film forming technique such as a plasma CVD method, and the front and back pad electrodes (2a) are formed using a well-known photolithography technique.

（６ａ）を形成することによって貫通する導電部７ｃ　
）が得られる。Conductive portion 7c that penetrates by forming (6a)
) is obtained.

各半導体基板（ｌａ）、（ｘｂ）、（１ｃ）を積層する
際には第１の半導体基板（１ａ）の裏面パッド電極（６
ａ）と第２の半導体基板（１ｂ）の表面パッド電極（２
ｂ）との間および、第２の半導体基板（１ｂ）の裏面パ
ッド電極（６ｂ）と第３の半導体基板（１ｃ）の表面パ
ッド電極（２Ｃ）との間を低融点はんだで接着積層すれ
ばよい０ このようにすれば、第１の半導体基板（１ａ）の表面パ
ッド電極（２ａ）とチップマウント（３）の外部端子（
４）とを金属＃　（５）で結べば、すべての半導体基板
（１ａ）　、　（ｌｂ）　、　（ｌｃ　）との接続が達
成できる。When stacking each semiconductor substrate (la), (xb), (1c), the back pad electrode (6) of the first semiconductor substrate (1a) is
a) and the surface pad electrode (2) of the second semiconductor substrate (1b).
b) and between the back pad electrode (6b) of the second semiconductor substrate (1b) and the front pad electrode (2C) of the third semiconductor substrate (1c) with low melting point solder. Good 0 By doing this, the surface pad electrode (2a) of the first semiconductor substrate (1a) and the external terminal (
4) with metal # (5), connections with all semiconductor substrates (1a), (lb), and (lc) can be achieved.

なお、上記実施例では積層される半導体基板は同一寸法
の場合を示したが、寸法の異なる半導体基板を積層して
もよく、また積層枚数も実施例の３枚に限らず２枚以上
例枚であってもよい。更に、貫通の導電部を孔あけとＣ
ｖＤ皮膜による被覆方式を用いて形成した場合を示した
が、その他の任意の方法で形成してもよい。In the above embodiment, the semiconductor substrates to be stacked have the same size, but semiconductor substrates with different dimensions may be stacked, and the number of stacked boards is not limited to three as in the embodiment, but may be two or more. It may be. Furthermore, the conductive part of the through hole is drilled and C
Although the case of forming using the vD film coating method has been shown, it may be formed using any other method.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、この発明の半導体装置では、半導
体基板の表裏対応位置にパッド電極を設け、これら表裏
両パッド電極間を半導体基板を貫通する導電部で接続し
ておき、このような半導体基板を複数枚積み重ねて立体
化したので、平面的な広がりを大きくすることなく大規
模集積化が可能である。As explained above, in the semiconductor device of the present invention, pad electrodes are provided at positions corresponding to the front and back sides of a semiconductor substrate, and the front and back pad electrodes are connected by a conductive portion penetrating the semiconductor substrate. By stacking multiple sheets to create a three-dimensional structure, large-scale integration is possible without increasing the planar area.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の半導体装置の構成を示す斜視図、第２図
はこの発明の一実施例の構成を示す斜視図、第３図は第
２図のＩ−ｌ［線における拡大部分断面図である。 図において、（ｌａ）　、　（ｌｂ）　、　（１０”）
は半導体基板、（ｚａ）、（２ｂ）、（２ｃ）は表面パ
ッド電極、（ａａ）、　（６ｂ）、（６ｃ　）は裏面パ
ッド電極、（’７ａ）、　（’７ｂ）　、（７ｃ）は貫
通導電部である。 なお、図中同一符号は同一または相当部分を示す。FIG. 1 is a perspective view showing the structure of a conventional semiconductor device, FIG. 2 is a perspective view showing the structure of an embodiment of the present invention, and FIG. 3 is an enlarged partial cross-sectional view taken along the line I-I in FIG. It is. In the figure, (la), (lb), (10”)
are semiconductor substrates, (za), (2b), (2c) are front pad electrodes, (aa), (6b), (6c) are back pad electrodes, ('7a), ('7b), (7c) are This is a through conductive part. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] （１）半導体基板の表面および裏面の互いに対応する位
置にパッド電極を設けるとともに上記半導体基板を貫通
して上記表面および裏面のパッド電極の間を接続する導
電部を形成し、複数枚の上記半導体基板を一つの上記半
導体基板の裏面のパッド電極と他の上記半導体基板の表
面のパッド電極とが順次接するように積み重ねるように
したことを特徴とする半導体装置。(1) Pad electrodes are provided at positions corresponding to each other on the front and back surfaces of the semiconductor substrate, and a conductive portion is formed to penetrate the semiconductor substrate and connect between the pad electrodes on the front and back surfaces, and A semiconductor device characterized in that substrates are stacked such that a pad electrode on the back surface of one of the semiconductor substrates and a pad electrode on the front surface of the other semiconductor substrate are sequentially in contact with each other.
JP59144728A 1984-07-10 1984-07-10 Semiconductor device Pending JPS6122660A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59144728A JPS6122660A (en) 1984-07-10 1984-07-10 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59144728A JPS6122660A (en) 1984-07-10 1984-07-10 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6122660A true JPS6122660A (en) 1986-01-31

Family

ID=15368941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59144728A Pending JPS6122660A (en) 1984-07-10 1984-07-10 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6122660A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5191224A (en) * 1987-04-22 1993-03-02 Hitachi, Ltd. Wafer scale of full wafer memory system, packaging method thereof, and wafer processing method employed therein
US5202754A (en) * 1991-09-13 1993-04-13 International Business Machines Corporation Three-dimensional multichip packages and methods of fabrication

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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