JPH06268151A - Semiconductor device - Google Patents

Abstract

PURPOSE:To achieve a high-density mounting operation by a method wherein electrode terminals on the surface of each semiconductor chip are extracted to the surface of a recessed part formed at the peripheral edge part on the back of each chip, chips are stacked and common electrode terminals are connected respectively. CONSTITUTION:A recessed part 2 is formed on the back of a semiconductor chip 1, and a protrusion part 1a is formed at the peripheral edge part on the back of the semiconductor chip 1. Electrode terminals for each semiconductor chip 1 are extracted to the protrusion part 1a, and a plurality of semiconductor chips 1 are stacked. Thereby, active regions 1c for the semiconductor chips 1 do not come into contact with other semiconductor chips 1, and common electrode terminals are connected mutually. As a result, gaps between the semiconductor chips 1 can be reduced, a mounting height can be made small and only the area of the semiconductor chips 1 is sufficient as an area. Thereby, a high-density mounting operation can be performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device. More specifically, the present invention relates to a multi-chip module type semiconductor device such as a memory module in which a large number of semiconductor chips on which the same circuit is formed are arranged and common electrode terminals are connected.

[0002]

2. Description of the Related Art Conventionally, a module type semiconductor device in which a large number of semiconductor elements or chips having the same circuit are arranged is used for a memory device or the like. These semiconductor devices require a large number of elements or chips to be arranged in the same package as the functions of electronic devices have become more sophisticated and complex in recent years.
64 columns are arranged. Moreover, it is necessary to reduce the mounting area due to the demand for miniaturization of electronic devices.

A conventional multi-chip module type semiconductor device has a structure as shown in FIG.

FIG. 3A shows a WB in which a plurality of semiconductor chips 21 are two-dimensionally arranged on a wiring board or the like at regular intervals.
It is a multi-chip module of the type, and is easy to manufacture, but the mounting area is large.

In FIG. 3B, the back surfaces (that is, the surfaces opposite to the active regions) of the two semiconductor chips 21 are adhered and sealed with resin or the like. A lead wire 22 is led out from the front side (active region portion) of each semiconductor chip, and common electrode terminals are connected and led out to the outside of the package.

Compared with the above-mentioned method, twice the number of semiconductor chips will be arranged in the same area, but only two semiconductor chips can be stacked in one package, and higher integration cannot be achieved. , Causing an increase in package thickness,
The manufacturing method also becomes complicated. .

The structure shown in FIG. 3C is a semiconductor chip.
Electrical wiring is connected to each electrode terminal of 21 by a TAB 23 holding a flexible film, and a common electrode terminal is connected to the other end side of the TAB 23 whose one end side is connected to each semiconductor chip 21.

Reference numeral 24 is a film for holding the lead portion, and 25 is a resin for protecting the chip surface.

[0009]

A conventional multi-chip module type semiconductor device is formed with the structure as described above. However, in the structure in which the semiconductor chips are arranged on the substrate, there is a problem that the mounting area becomes large because the semiconductor chips are arranged in a plane.

Further, in the structure in which the back surfaces of two chips are adhered to each other, the mounting area is about half that of a packaged product on which one semiconductor chip is mounted, but the package area is required at the time of mounting. Unable to achieve integration of two or more.

Further, in the structure in which the respective electrode terminals are connected by the TAB and the semiconductor chips are stacked, two or more can be stacked, but the stacking connection method of the lead parts becomes complicated and the mounting height is increased by the film and the lead parts. Becomes higher and the volume becomes larger.

It is an object of the present invention to provide a small-sized and highly integrated semiconductor device by solving such a problem and suppressing the mounting area and volume of the multi-chip module type semiconductor device.

[0013]

The semiconductor device of the present invention comprises:
A multi-chip module type semiconductor device in which a plurality of semiconductor chips of the same type are arranged and common electrode terminals are connected to each other, wherein a convex portion is provided on a peripheral portion of the back surface of the semiconductor chip and The electrode terminals are led out to the surface of the convex portion, and the common electrode terminals are connected to each other by stacking the semiconductor chips.

[0014]

According to the present invention, since the convex portion is provided on the peripheral portion of the back surface of each semiconductor chip and the electrode terminal of each semiconductor chip is led out to the convex portion, a plurality of semiconductor chips are directly stacked to form a semiconductor. The common electrode terminals are connected to each other without the active area of the chip contacting other semiconductor chips. As a result, since the gap between the semiconductor chips can be reduced, the mounting height can be reduced, and the area is limited to the area of the semiconductor chip, and a semiconductor device having the smallest mounting area and volume can be obtained.

[0015]

The present invention will be described below with reference to the drawings. 1A is a sectional view of an embodiment of a semiconductor device of the present invention, FIG. 1B is a partially enlarged view of FIG. 1A, and FIG. 1C is a plan view of FIG. FIG. 2 is a diagram illustrating a connection example of electrode terminals when semiconductor chips are stacked.

As shown in FIG. 1A, the semiconductor chip 1
On the back surface (the side that is not the active region portion; the lower side in FIG. 1A) of the semiconductor chip 1, the concave portion 2 is provided, so that the convex portion 1a is formed on the peripheral portion of the rear surface of the semiconductor chip 1. This convex portion 1a
The reason for forming is that the active region portion 1c of the semiconductor chip 1 is formed with electrodes and the like, and when the semiconductor chips 1 are stacked, they do not come into contact with the upper semiconductor chip 1 to cause physical damage. To do so. Therefore,
As shown in (b), the height H of the convex portion 1a depends on the active region 1
It only needs to have the height of c, and it is usually formed to have a thickness of about 5 to 10 μm. In addition, as shown in FIG. 1C, a vertical through hole 3 penetrating the semiconductor chip 1 is formed on the peripheral portion of the semiconductor chip 1 where the convex portion 1a is formed. About 60 pieces are provided, the number of which depends on the function of the semiconductor chip, but the diameter is about 0.1 to 0.
About 5 mm is preferable. If it is too large, a large number of terminals cannot be obtained and the chip area also becomes large. Also, if it is too small, the inside cannot be plated. Both the concave portion 2 and the through hole 3 can be formed by wet etching using a HF-HNO ₃ based etching solution or an alkaline etching solution, or a laser light irradiation method.

This through hole 3 is, as shown in FIG.
The electrode terminals on the front surface side of the semiconductor chip 1 are led out to the back surface side by electrical wiring and are connected to the lower semiconductor chip 1, and a conductive film 5 is provided inside the through hole 3 via an insulating film 4. It is provided by electroless plating or the like. The insulating film 4 insulates the semiconductor chip 1 from the conductive film 5, and is provided by depositing a silicon oxide film, a silicon nitride film, or the like by a CVD method, an oxidation method, or the like. Further, the conductive film 5 is provided with a base metal such as titanium, tantalum, tungsten, and nickel in an amount of about 0.1 to 5 μm to improve adhesion and prevent diffusion, and a metal such as gold is added to the surface to prevent oxidation of about 0.05 to 2 μm. It is preferably provided. This through hole 3
A module in which the semiconductor chips 1 are stacked can be formed in a small size by providing the conductive film 5 therein, but a conductive film can be provided around the semiconductor chip 1 so that the electrode terminals on the front surface of the semiconductor chip can be led out to the back surface side. .

In order to manufacture this semiconductor device, first, a semiconductor circuit including memory cells and the like is formed in the state of a semiconductor wafer by a normal manufacturing process.

Next, on the back surface side of the semiconductor wafer, etching is performed using an HF-HNO ₃ -based or alkaline-based etching solution so that the peripheral portion has a width of about 300 to 800 μm when it is cut into semiconductor chips. , The recess 2 is formed. Subsequently, masking is applied to a portion other than the place where the through hole 3 is formed, and the same etching is performed to form the through hole 3 in the peripheral portion when the semiconductor chip 1 is formed.

Further, silicon oxide or the like is deposited on the entire surface of the through hole 3 by the CVD method, or 0.1% by the oxidation method.
The insulating film 4 having a thickness of about 0.5 μm is provided.

Next, the conductive film 5 is provided in the through hole 3 and on the upper and lower surfaces thereof by electroless plating. At this time, the conductive film 5 on the upper and lower surfaces is masked so as not to protrude from the insulating film 4, and each through hole 3 is connected to the conductive film 5 with an electrode terminal. As a specific example, Ni-at 80 to 90 ° C
Electroless nickel plating is performed with a P-based plating solution to form a nickel layer with a thickness of 0.1 to 2 μm, and then Au plating with a thickness of 0.1 to 1.0 μm is formed as the outermost layer by electroless plating at 80 to 90 ° C. . After that, the conductive film 5 was formed by washing with pure water at room temperature for about 10 minutes.

By dicing the semiconductor wafer on which the semiconductor circuit and the conductive film are formed in this manner, each semiconductor chip 1 is obtained. This semiconductor chip 1 is shown in FIG.
As shown in (a), stack in the same direction and
By thermocompression bonding at a temperature of ° C., it is possible to form a multi-chip module in which the entire portion of the conductive film 5 is bonded and the common electrode is connected. A reliable connection can be obtained by applying ultrasonic waves during this bonding.

Here, electrode terminals common to each semiconductor chip, such as a data bus or an address bus, are formed at the same position on the semiconductor chip so that they can be connected in parallel by stacking and crimping. It is necessary to lead out the signal electrode terminals separately. In this case, for example, as shown in FIGS.
11 to 14 specific electrode terminals (for example, 51a, 52b, 53c, 54)
d) are provided so as to be displaced, and conductive films of other semiconductor chips corresponding to the terminals (for example, 52a, 53a for 51a,
54a) is a terminal that is not connected to any part of the semiconductor chip, and after stacking,
As shown in FIG. 2E, the semiconductor chips 11, 12, 13,
The 14 unique electrode terminals 51a, 52b, 53c, 54d can be led out to the same surface. In FIG. 2, another conductive film 5
Indicates common electrodes of the respective semiconductor chips.

In the above embodiment, the convex portion is formed on the peripheral edge portion by providing the concave portion on the back surface of the semiconductor chip, but a spacer may be interposed without forming the concave portion on the rear surface. In this case, a through hole and a conductive film may be similarly provided by interposing an ordinary semiconductor or insulating film, or an anisotropic conductive adhesive film may be provided only at the peripheral portion to conduct only the conductive film portion. It can also be planned.

By using the semiconductor device having the above-mentioned structure, the stacking interval between chips is 0.3 to 1.
The required height was about 0 mm, but the height of the convex portion of about 5 to 10 μm is sufficient, and as a result, the mounting height becomes about 20 to 50% of the conventional level when the same number of semiconductor chips are stacked.

[0026]

According to the present invention, a semiconductor chip of a multi-chip module type is provided in which a convex portion is provided on a peripheral portion of a semiconductor chip and stacked and pressure-bonded to prevent contact with another chip and common electrode terminals are connected. The device can be obtained. Therefore, not only the occupied area but also the mounting height is significantly reduced,
High-density mounting is possible and a small semiconductor device can be obtained. As a result, it can be used in the field of connecting a large number of the same chips such as a memory module, which greatly contributes to downsizing of electronic devices.

[Brief description of drawings]

FIG. 1 is an explanatory view of an embodiment of a semiconductor device of the present invention, (a) is a sectional view, (b) is a partially enlarged view of (a), (c).
Is a plan view.

FIG. 2 is a diagram illustrating a connection example of electrode terminals specific to each chip when semiconductor chips are stacked.

FIG. 3 is a schematic explanatory view showing an example of a package of a conventional multi-chip module type semiconductor device, (a) of FIG.
An example of a dimensional package, (b) is a package in which two chips are bonded together, and (c) is an example of a stacked package using TAB.

[Explanation of symbols]

 1 semiconductor chip 1a convex portion 5 conductive film

Claims (1)

[Claims] 1. A multi-chip module type semiconductor device in which a plurality of semiconductor chips of the same type are arranged, and common electrode terminals are connected to each other, wherein a convex portion is provided on a peripheral portion of a back surface of the semiconductor chip. A semiconductor device in which electrode terminals on the surface of the semiconductor chip are led out to the surface of the convex portion and the common electrode terminals are connected by stacking the semiconductor chips.