JPH01130270U - - Google Patents
Info
- Publication number
- JPH01130270U JPH01130270U JP2607988U JP2607988U JPH01130270U JP H01130270 U JPH01130270 U JP H01130270U JP 2607988 U JP2607988 U JP 2607988U JP 2607988 U JP2607988 U JP 2607988U JP H01130270 U JPH01130270 U JP H01130270U
- Authority
- JP
- Japan
- Prior art keywords
- conductors
- chip
- chip substrate
- jumper array
- insulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims description 2
- 239000000919 ceramic Substances 0.000 description 2
Landscapes
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
- Multi-Conductor Connections (AREA)
Description
第１図は本考案による第１の実施例を示すもの
で、セラミツク基板面に複数本の導電体を施して
成るチツプジヤンパーアレーの斜視図、第２図は
同じく第２の実施例を示すもので複数本の導電体
が交差して成るチツプジヤンパーアレーの斜視図
である。
図中、１……セラミツク基板、２……導電体、
３……絶縁体 である。
Fig. 1 shows a first embodiment of the present invention, which is a perspective view of a chip jumper array formed by applying a plurality of conductors on the surface of a ceramic substrate, and Fig. 2 shows a second embodiment. 1 is a perspective view of a chip jumper array made up of a plurality of intersecting conductors. In the figure, 1...ceramic substrate, 2...conductor,
3...It is an insulator.
Claims (1)
面にわたつて連なる１本あるいは複数本の導電体
を形成して成ることを特徴とするチツプジヤンパ
ーアレー。 (2) チツプ基板面に複数本の導電体を交差させ
、該交差する導電体間に絶縁体を施して導体短絡
を防止して成ることを特徴とする請求項１記載の
チツプジヤンパーアレー。[Claims for Utility Model Registration] (1) A chip jumper array characterized by forming one or more conductors extending from the top surface of a chip substrate to at least two side surfaces. (2) A chip jumper array according to claim 1, characterized in that a plurality of conductors are made to intersect on the surface of the chip substrate, and an insulator is provided between the intersecting conductors to prevent conductor short circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2607988U JPH01130270U (en) | 1988-02-29 | 1988-02-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2607988U JPH01130270U (en) | 1988-02-29 | 1988-02-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01130270U true JPH01130270U (en) | 1989-09-05 |
Family
ID=31247378
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2607988U Pending JPH01130270U (en) | 1988-02-29 | 1988-02-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01130270U (en) |
-
1988
- 1988-02-29 JP JP2607988U patent/JPH01130270U/ja active Pending