JPH01130192A - Driving of plasma display device - Google Patents

Driving of plasma display device

Info

Publication number
JPH01130192A
JPH01130192A JP62289903A JP28990387A JPH01130192A JP H01130192 A JPH01130192 A JP H01130192A JP 62289903 A JP62289903 A JP 62289903A JP 28990387 A JP28990387 A JP 28990387A JP H01130192 A JPH01130192 A JP H01130192A
Authority
JP
Japan
Prior art keywords
period
voltage
state
electrode
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62289903A
Other languages
Japanese (ja)
Other versions
JP2576158B2 (en
Inventor
Hiroshi Haneda
羽田 寛
Masahisa Hosono
細野 昌久
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62289903A priority Critical patent/JP2576158B2/en
Publication of JPH01130192A publication Critical patent/JPH01130192A/en
Application granted granted Critical
Publication of JP2576158B2 publication Critical patent/JP2576158B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Abstract

PURPOSE: To extend the range of driving voltage and to boost the voltage by impressing the same pulselike voltage as that of a nondata period in the initial partial period of an address state and setting up the frequency of pulselike voltage impressed to scanning electrodes in a hold state to a level higher than the frequency of an address state. CONSTITUTION: One scanning period H includes a period (a) for executing display in an address state and a period (b) for executing display in a hold state and the same pulselike voltage as that of a nondata period is impressed in the initial partial period (c) of the address state independently of the existence of data. The frequency of pulselike voltage impressed to scanning electrodes in the hold state is set up to a level higher than the frequency of the address state. Consequently the driving voltage can be extended at its range and boosted.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、プラズマディスプレイの駆動方法に関し、特
に、ACリフレッシュ形プラズマディスプレイ(FDP
)の駆動方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for driving a plasma display, and particularly relates to a method for driving a plasma display (AC refresh type plasma display).
).

〔従来の技術〕[Conventional technology]

従来、この種のACリフレッシュ形プラズマデイスフレ
イ(FDP)の駆動方法として、絶縁体及び、放電空間
を介して互いに対向する外部電極群のいずれか一方の電
極群に印加される電圧波形が、時分割されたパルス状で
あり、他方の電極群には、前記一方の電極群に印加され
た電圧波形に対して、点灯させる時には、逆位相のパル
ス電圧を印加し、点灯させない時には、同位相の電圧を
印加することによって安定な動作を示すことが特公昭5
5−48318号公報に示されている。
Conventionally, as a driving method for this type of AC refresh type plasma display (FDP), the voltage waveform applied to either one of the insulator and the external electrode group facing each other through the discharge space is The voltage waveform is divided into divided pulses, and when the voltage waveform applied to the one electrode group is turned on, a pulse voltage of the opposite phase is applied to the other electrode group, and when the voltage waveform is not turned on, a pulse voltage of the same phase is applied to the other electrode group. It was discovered in the 1970s that it demonstrated stable operation by applying voltage.
5-48318.

また、一方の走査電極に電力放電開始電圧より高いパル
ス状電圧を印加し、従来のフェーズセレクト法(特公昭
55−48318)と同様に表示の有無に従って、他方
の電極に同相、逆相のパルス状電圧を印加し、放電させ
るべき放電セルは放電させ、放電させない放電セルは放
電させない状態を予め作り、続いて他方の電極のパルス
状電圧を除去して、一方の電極のみに印加されるパルス
状電圧で、その状態を持続させ、一方の電極のパルス状
電圧で非点灯セルが点灯する前に、従来のフェーズセレ
クト法と同様の状態に戻すことな繰り返すことによって
、消費電力の低減をはかる方法も提案されている。
In addition, a pulsed voltage higher than the power discharge starting voltage is applied to one scanning electrode, and in-phase and opposite-phase pulses are applied to the other electrode depending on whether or not to display, similar to the conventional phase selection method (Japanese Patent Publication No. 55-48318). A voltage is applied to the discharge cells that should be discharged, and discharge cells that are not to be discharged are not discharged. Then, the pulse voltage of the other electrode is removed, and the pulse voltage is applied only to one electrode. This method reduces power consumption by sustaining that state with a pulsed voltage of one electrode, and returning to the state similar to the conventional phase selection method before turning on non-lit cells with a pulsed voltage of one electrode. A method has also been proposed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の駆動方法では、同一絶縁体上に形成され
た電極群の各々の電極に点灯、非点灯に対応して逆位相
、同位相のパルス電圧を印加して駆動する方法であるた
め、電気的には、各々の電極間のストレー容量を介して
駆動回路が結合され、点灯、非点灯の状態が隣接した電
極間に生じた場合に、駆動回路の消費電力は最大になる
。さらに、A(lフレッシュFDPの輝度は、単位時間
に含まれるパルスの数によって決るが、パルスの数を増
加させる為、駆動周波数を高くすると、駆動回路の消費
電力の増大が起こる。また、さらに、データ側電極に透
明電極が用いられている場合には、この透明電極と電極
間のストレー容量による分布定数回路が形成され、駆動
回路の出力と、透明電極との先端の部分での波形、及び
電圧が異なるため、走査側パルス電圧とデータ側パルス
電圧に時間的ずれ及び電圧の変化が生じ、特公昭55−
48318で開示されている場合と異なる動作を示し、
駆動電圧範囲が狭くなる欠点があった。
In the conventional driving method described above, pulse voltages of opposite phase and the same phase are applied to each electrode of the electrode group formed on the same insulator in response to lighting and non-lighting. Electrically, the drive circuit is coupled through the stray capacitance between the respective electrodes, and the power consumption of the drive circuit is maximized when a lighting or non-lighting state occurs between adjacent electrodes. Furthermore, the brightness of A(l fresh FDP is determined by the number of pulses included in a unit time, but if the drive frequency is increased to increase the number of pulses, the power consumption of the drive circuit will increase. When a transparent electrode is used as the data side electrode, a distributed constant circuit is formed by the stray capacitance between the transparent electrode and the electrode, and the output of the drive circuit and the waveform at the tip of the transparent electrode, and voltage are different, there is a time lag and voltage change between the scanning side pulse voltage and the data side pulse voltage.
48318,
There was a drawback that the driving voltage range was narrow.

すなわち、駆動周波数の上限が決まっており、充分な輝
度を得ることが困難である欠点もあった。
That is, the upper limit of the driving frequency is fixed, and there is also the drawback that it is difficult to obtain sufficient brightness.

〔発明の従来技術に対する相違点〕[Differences between the invention and the prior art]

上述した従来の駆動方法に対し、本発明は、一走査期間
中にアドレス状態で表示を行わせる期間とホールド状態
で表示を行わせる期間とを含み、さらにアドレス状態は
、最初の一部の期間は、データの有無に関係なくデータ
の無いときと同じ一パルス状電圧を印加する期間であり
、ホールド状態で走査電極に印加されるパルス状電圧の
周波数を少なくともアドレス状態の周波数よりも高くす
るという独創的内容を有する。
In contrast to the conventional driving method described above, the present invention includes a period in which display is performed in an address state and a period in which display is performed in a hold state during one scanning period, and furthermore, the address state is set during an initial part of the period. is a period in which the same pulse-like voltage is applied regardless of the presence or absence of data as when there is no data, and the frequency of the pulse-like voltage applied to the scan electrode in the hold state is at least higher than the frequency in the address state. It has original content.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、上述した従来のACリフレッシュ形プラズマ
ディスプレイの駆動方法の欠点を除去した駆動方法を提
供するものである。すなわち、一走査期間中にアドレス
状態で表示を行わせる期間とホールド状態で表示を行わ
せる期間とを含み、さらにアドレス状態は、最初の一部
の期間は、データの有無に関係なくデータの無いときと
同じパルス状電圧を印加する期間であり、ホールド状態
で走査電極に印加されるパルス状電圧の周波数を少なく
ともアドレス状態の周波数よりも高くすることを特徴と
している。
The present invention provides a driving method that eliminates the drawbacks of the conventional AC refresh type plasma display driving method described above. In other words, one scanning period includes a period in which the display is performed in the address state and a period in which the display is performed in the hold state, and in addition, the address state includes a period in which the display is performed in the hold state. This is a period in which the same pulsed voltage as in the hold state is applied, and is characterized in that the frequency of the pulsed voltage applied to the scan electrode in the hold state is at least higher than the frequency in the address state.

〔実施例〕〔Example〕

次に、図面を参照して詳細に説明する。 Next, a detailed description will be given with reference to the drawings.

第1図は、本発明の第1の実施例の電圧配置のタイミン
グチャートである。第2図は、走査電極に印加されるパ
ルス状電圧のタイミングを説明するためのタイミングチ
ャートである。
FIG. 1 is a timing chart of voltage arrangement according to the first embodiment of the present invention. FIG. 2 is a timing chart for explaining the timing of pulsed voltages applied to the scanning electrodes.

本発明の駆動方法に用いられるプラズマディスプレイパ
ネルは誘電体で被覆された電極群をもつ二枚のガラス板
を、電極群が互いに対向し、それぞれの電極群は直交し
、交点が表示の発光点となるように設計されている。こ
のプラズマディスプレイパネルを駆動するには、一般に
、第2図ノ2−Eに示されている水平同期信号によりH
期間だけ第1の電極が選択され、第2図の2−Aに示さ
れる波高値■。をもつパルス状電圧が、第1の電極に印
加される。水平m個、垂直n個の電極をもつパネルの場
合には、第1の水平電極に対してn個の垂直電極が選択
され駆動される。
The plasma display panel used in the driving method of the present invention consists of two glass plates each having electrode groups covered with a dielectric, the electrode groups facing each other, each electrode group intersecting at right angles, and the intersection point being the light emitting point for display. It is designed to be. To drive this plasma display panel, generally the horizontal synchronizing signal shown in FIG.
The first electrode is selected only for a period of time, and the peak value ■ is shown in 2-A in FIG. A pulsed voltage having a value of 0 is applied to the first electrode. In the case of a panel having m horizontal electrodes and n vertical electrodes, n vertical electrodes are selected and driven relative to the first horizontal electrode.

次に、一定の期間(ブランキング期間)をおいて、第2
の電極が選択され、第1の電極と同様にH期間だけV。
Next, after a certain period (blanking period), the second
The electrode is selected and, like the first electrode, V is applied for the H period.

の波高値をもつパルス状電圧が、第2の電極に印加され
る。(第2図2−B参照)第3の電極には、第2の電極
にパルス。状電圧が印加された後パルス状電圧が印加さ
れ、以後順次この操作は繰り返えされ、垂直同期信号が
入ってくるまでの期間(V)続く。第2図2−Dの垂直
同期信号によって、第1の電極を選択できる状態にもど
される。
A pulsed voltage having a peak value of is applied to the second electrode. (See Figure 2 2-B) The third electrode is pulsed to the second electrode. After the pulse-like voltage is applied, a pulse-like voltage is applied, and this operation is sequentially repeated thereafter for a period (V) until the vertical synchronizing signal is input. The state in which the first electrode can be selected is returned by the vertical synchronizing signal shown in FIG. 2 2-D.

即ち、本方法の走査は、水平同期信号によって順次走査
され、全水平電極が走査された後に入力される垂直同期
信号によってもとの状態に復帰される。垂直同期信号は
、表示のリフレッシュ周波数と一致し、一般には60サ
イクル以上に選ばれる。一方、垂直同期信号の1期間に
含まれる水平同期信号の数が走査本数に一致するが、一
般には、走査本数とパネルの走査電極数とは一致せず、
走査本数がパネルの走査電極数よりも多い。
That is, in the scanning method of this method, the horizontal synchronizing signal is used to scan sequentially, and after all the horizontal electrodes have been scanned, the original state is restored by the input vertical synchronizing signal. The vertical synchronization signal matches the refresh frequency of the display and is generally chosen to be 60 cycles or more. On the other hand, although the number of horizontal synchronization signals included in one period of the vertical synchronization signal matches the number of scan lines, generally the number of scan lines does not match the number of scan electrodes of the panel.
The number of scanning lines is greater than the number of scanning electrodes on the panel.

第1図1−Aは、第1行電極に印加されるパルス状電圧
を示し、第1図の1−B、1−Cはそれぞれ第m列、n
列電極に印加されるパルス状電圧を示したものである。
1-A in FIG. 1 shows a pulsed voltage applied to the first row electrode, and 1-B and 1-C in FIG. 1 indicate the m-th column and n-th column, respectively.
It shows the pulsed voltage applied to the column electrodes.

第1図の1−D、1−Eはそれぞれ、第1行電極と第m
列電極、第n列電極との交点に形成される放電発光点(
1行2m列)セル、(1行、n列)セルに印加される電
圧波形を示したものである。
1-D and 1-E in FIG. 1 are the first row electrode and the mth row electrode, respectively.
A discharge light emitting point (
The voltage waveforms applied to the cell (row 1, column n) and the cell (row 1, column n) are shown.

第m列電極に印加されている電圧波形は、最初の2発を
除いて、第1行電極に印加されている電圧波形と逆相で
あるから、(1、行2m列)セルは、点灯モードである
The voltage waveform applied to the m-th column electrode is in opposite phase to the voltage waveform applied to the first-row electrode, except for the first two shots, so the cell (1st row, 2nd column) is lit. mode.

一方、第n列電極に印加されているパルス状電圧は、第
1行電極に剛化されているパルス状電圧と同相であるか
ら(1行、n列)セルは非点灯モード、即ち、消灯モー
ドである。(1行2m列)セルに印加されるパルス状電
圧は、第1行電極と第m列電極に印加されるパルス状電
圧の電位差で表され、第1図の1−Dの波形となる。(
1行、n列)セルに印加されるパルス状電圧も同様に電
位差で表すと第1図1−Eのようになる。
On the other hand, since the pulsed voltage applied to the n-th column electrode is in phase with the pulsed voltage stiffened to the first row electrode (1st row, nth column), the cell is in the non-lighting mode, that is, it is turned off. mode. The pulsed voltage applied to the cell (row 1 and column 2m) is expressed by the potential difference between the pulsed voltage applied to the first row electrode and the mth column electrode, and has a waveform of 1-D in FIG. (
Similarly, the pulsed voltage applied to the cell (row 1, column n) is expressed as a potential difference as shown in FIG. 1-E.

H期間中のa期間の動作は特公昭55−48318と全
く同じであり、この期間を本発明ではアドレス状態と定
義する。一方、H期間中のb期間に点灯セル、消灯セル
に印加される電圧は第1図1−D、1−Eで示されるよ
うに、点灯。
The operation in period a during period H is exactly the same as in Japanese Patent Publication No. 55-48318, and this period is defined as the address state in the present invention. On the other hand, the voltages applied to the lit cells and unlit cells during the b period of the H period are turned on, as shown in FIG. 1-D and 1-E.

消灯に関係なく全く同じであり、この期間をホールド状
態と定義する。
This is exactly the same regardless of whether the light is turned off, and this period is defined as a hold state.

まず、アドレス状態における動作は、プラズマディスプ
レイパネルの電極間に、パルス状電圧を印加して躍動す
るにあたって、一方の電極のみにパルス電圧を印加して
他方の電極を0電位に保って、電極間で放電を起こさせ
る時、プラズマディスプレイパネル内の一つの放電セル
が、放電する電圧を最小里方放電開始電圧(VDmiH
)、プラズマディスプレイパネルの全てのセルが、放電
する電圧を最大放電開始電圧(VDmax)と定義した
場合、プラズマディスプレイの一方の電極に、VDmi
nよりも高く、VDmaxよりも低いパルス状電圧(、
V o )を印加しておき、他方の電極に、それと逆相
、同相のパルス状電圧(vl)を印加すルト、VDmi
n>1Vol  lV+117)条件が満たされると放
電は停止しVDmax<l VOl + l V、 l
の条件が満たされると放電を開始する。
First, the operation in the address state is to apply a pulsed voltage between the electrodes of the plasma display panel to make it move. When causing a discharge, one discharge cell in the plasma display panel sets the discharge voltage to the minimum discharge starting voltage
), if the voltage at which all cells of the plasma display panel discharge is defined as the maximum discharge starting voltage (VDmax), one electrode of the plasma display has VDmi
A pulsed voltage higher than n and lower than VDmax (,
VDmi) is applied, and a pulsed voltage (vl) of the opposite phase and the same phase is applied to the other electrode.
n>1Vol lV+117) When the conditions are met, the discharge stops and VDmax<l VOl + l V, l
Discharge starts when the following conditions are met.

ホールドモードは、第1図1−D、1−Eの(b)期間
の電圧波形で示されているように振幅が(V o )で
あるパルス状電圧が点灯、消灯に関係なく印加され、ホ
ールド状態に先行して印加されるアドレス状態で作り出
された状態を、この期間中維持して、表示を行なうとす
るものである。
In the hold mode, as shown in the voltage waveforms of periods (b) in FIGS. 1-D and 1-E, a pulsed voltage having an amplitude of (V o ) is applied regardless of whether the light is on or off. The state created by the address state applied prior to the hold state is maintained during this period for display.

即ち、アドレス状態で点灯状態の(1行2m列)のセル
は、(a)期間中に放電し、放電で発生した荷電粒子で
セル中が満たされているため、アドレス状態よりも低い
電圧が印加されているホールド状態でも容易に放電が起
動する。
In other words, the cell (1st row, 2m column) that is lit in the address state discharges during period (a), and the cell is filled with charged particles generated by the discharge, so the voltage is lower than that in the address state. Discharge starts easily even in the hold state where the voltage is applied.

一方アドレス状態で非点灯状態の(1行、n列)セルは
アドレス状態で期間に印加電圧が放電開始電圧よりも低
く、(1行、n列)のセルには荷電粒子はなく、放電は
C期間中に開始しないで、続くb期間中に印加されてい
る電圧で放電を開始するまでにはある時間が必要であり
、b期間を適当に選択するとホールド状態で放電開始し
ない電圧を定めることができる。
On the other hand, in the cell (1st row, n column) that is not lit in the address state, the voltage applied during the period in the address state is lower than the discharge start voltage, and there are no charged particles in the cell (1st row, n column), and the discharge does not occur. A certain amount of time is required to start discharging at the voltage applied during period b without starting during period C, and if period b is selected appropriately, it is possible to determine the voltage at which discharge will not start in the hold state. Can be done.

次に本発明により、新たに設けられた第1図におけるC
の期間について説明する。この期間は、第1図1−B、
1−Cのように、データの有無に関係なく、消灯のモー
ドのパルスが印加される。
Next, according to the present invention, C in FIG. 1 is newly provided.
The period will be explained. During this period, Figure 1 1-B,
As in 1-C, a pulse for the light-off mode is applied regardless of the presence or absence of data.

このとき、全てのデータ側電極に同じパルスが印加され
るわけであるから、データ側電極間のストレー容量によ
る影響が、無視できるようになり、駆動回路の出力と、
電極の先端部分での波形及び電圧の違いは、少くなる。
At this time, since the same pulse is applied to all data-side electrodes, the influence of stray capacitance between data-side electrodes can be ignored, and the output of the drive circuit and
The difference in waveform and voltage at the tip of the electrode is reduced.

さらに、この期間、全ての放電セルが、放電を停止する
為、隣接セルからの放電のひろい込みもなくなる。結局
、C,C期間のアドレス状態で、従来の駆動方式に比べ
、放電すべきセルは、C期間の消灯モードのパルスの為
、少し放電しにくくなるが、放電してはいけないセルは
、C期間で、放電が、完全に停止する為、隣接セルから
のひろい込みがなくなる。つまり、表示上、誤灯する電
圧が、高くなることにより、駆動電圧を広くかつ高くす
ることができる。
Furthermore, during this period, all the discharge cells stop discharging, so there is no spread of discharge from adjacent cells. In the end, in the address state of the C and C periods, compared to the conventional drive method, cells that should be discharged are a little more difficult to discharge due to the pulse of the turn-off mode in the C period, but cells that should not be discharged are Since the discharge completely stops during this period, there is no spread from adjacent cells. In other words, by increasing the voltage that causes erroneous lighting on display, the drive voltage can be widened and increased.

また、一般に、パルスの周波数を高くすると、駆動電圧
の出力状態をつくるスイッチング動作のスピードにより
、走査側パルス電圧とデータ側パルス電圧の時間的ずれ
を無くすのは、むずかしくなってしまい、誤灯する電圧
が低くなってしまう。
Additionally, in general, when the pulse frequency is increased, it becomes difficult to eliminate the time lag between the scan-side pulse voltage and the data-side pulse voltage due to the speed of the switching operation that creates the output state of the drive voltage, resulting in erroneous lighting. The voltage becomes low.

しかし、本発明によれば、アドレス状態の周波数を高く
して、誤灯電圧が低くなっても、C期間に消去パルスを
入れることにより、それ以上に、誤灯電圧を高くするこ
とができ、輝度アップをはかることができる。一方、本
発明により、b期間のホールド状態の周波数を高くする
ことにより、輝度アップをはかることができる。このと
き、さらに、C,C期間の周波数を低くすることにより
、データ側電極と電極間のストレーで形成される時定数
よりも下げることによってパネル全体に回路の出力波形
とほぼ同じ波形を与えることができて、動作が安定にな
る効果もある。尚、第1図1−Hにおいて、消去パルス
の次に細幅のパルスが描かれているが、これは、本発明
とは無関係であり、また、あってもなくても、同じ駆動
電圧の範囲という結果を得た。
However, according to the present invention, even if the frequency of the address state is increased and the false lighting voltage is low, the false lighting voltage can be further increased by inserting an erase pulse in the C period. Brightness can be increased. On the other hand, according to the present invention, brightness can be increased by increasing the frequency of the hold state during period b. At this time, by further lowering the frequency of the C and C periods, it is possible to lower the time constant formed by the data-side electrode and the stray between the electrodes, thereby giving the entire panel a waveform that is almost the same as the output waveform of the circuit. This also has the effect of making the operation more stable. Although a narrow pulse is drawn next to the erase pulse in FIG. I got a range result.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、一走査期間中にアドレス
状態で表示を行わせる期間とホールド状態で表示を行わ
せる期間とを含み、さらにアドレス状態は、最初の一部
の期間は、データの有無に関係なくデータの無いときと
同じパルス状電圧を印加する期間であり、ホールド状態
で走査電極に印加されるパルス状電圧の周波数を少なく
ともアドレス状態の周波数よりも高くすることにより、
駆動電圧の範囲を広く、かつ高くすることができる。ま
た、それに伴い、輝度のアップ、生産歩留りの向上をは
かることができる。
As explained above, the present invention includes a period in which display is performed in an address state and a period in which display is performed in a hold state during one scanning period, and furthermore, in the address state, during the first part of the period, data is not displayed. This is the period in which the same pulsed voltage as when there is no data is applied regardless of the presence or absence of data, and by making the frequency of the pulsed voltage applied to the scan electrode in the hold state at least higher than the frequency in the address state,
The driving voltage range can be widened and increased. Additionally, it is possible to increase brightness and improve production yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の第1の実施例の印加電圧波形を示し
たものである。第2図は、走査電極に印加されるパルス
状電圧の状態を示したものである。 1−A、2−A・・・・・・第1行の走査電極に印加さ
れるパルス状電圧、1−B・・・・・・第m列のデータ
電極に印加されるパルス状電圧、1−C・・・・・・第
n列のデータ電極に印加されるパルス状電圧、1−D・
・・・・・(1行1m列)セルに印加される電圧の状態
、1−E・・・・・・(1行、n列)セルに印加される
電圧の状態、2−B・・・・・・第2行の走査電極に印
加されるパルス状電圧、2−C・・・・・・第3行の走
査電極に印加されるパルス状電圧、2−D・・・・・・
垂直同期信号、2−E・・・・・・水平同期信号。 代理人 弁理士  内 原   晋 第1図 第2区
FIG. 1 shows applied voltage waveforms in a first embodiment of the present invention. FIG. 2 shows the state of the pulsed voltage applied to the scanning electrodes. 1-A, 2-A... Pulse voltage applied to the scan electrode of the first row, 1-B... Pulse voltage applied to the data electrode of the m-th column, 1-C... Pulse voltage applied to the n-th column data electrode, 1-D.
...(1st row, 1m column) State of the voltage applied to the cell, 1-E...(1st row, nth column) State of the voltage applied to the cell, 2-B... ... Pulse voltage applied to the second row scan electrode, 2-C... Pulse voltage applied to the third row scan electrode, 2-D...
Vertical synchronization signal, 2-E...Horizontal synchronization signal. Agent: Susumu Uchihara, Patent Attorney, Figure 1, Ward 2

Claims (1)

【特許請求の範囲】 電極が誘電体で被覆されているプラズマディスプレイパ
ネルの一方の走査電極群に時分割的に順次電圧を印加し
、走査しておき、それぞれの走査電極に印加される電圧
に同期して、他のデータ側電極群にデータの有無にした
がって電圧を印加して駆動するプラズマディスプレイの
リフレッシュ駆動方法に於いて、一走査期間中にアドレ
ス状態で表示を行わせる期間とホールド状態で表示を行
わせる期間とを含み、さらにアドレス状態は、最初の一
部の期間は、データの有無に関係なくデータの無いとき
と同じパルス状電圧を印加する期間であり、ホールド状
態で走査電極に印加されるパルス状電圧の周波数を少な
くともアドレス状態の周波数よりも高くしたことを特徴
とするプラズマディスプレイの駆動方法。 なおここで言うアドレス状態及びホールド状態は次のよ
うに定義する。即ち、一つの走査電極が選択されている
一走査期間中に走査電極に印加されるパルス状電圧と同
期し、しかも表示させるべきセルに対応するデータ側電
極には逆相、表示すべきでないセルに対応するデータ側
電極には同相のパルス状電圧を印加して表示を行う期間
の状態をアドレス状態、及びデータ側電極に印加されて
いたパルス状電圧をとめて、アドレス状態で作られた荷
電粒子と走査電極に印加されるパルス状電圧のみで駆動
される期間の状態をホールド状態と定義する。
[Claims] A voltage is sequentially applied in a time-division manner to one scanning electrode group of a plasma display panel whose electrodes are covered with a dielectric material to perform scanning, and the voltage applied to each scanning electrode is In a plasma display refresh drive method in which a voltage is applied to other data-side electrode groups in synchronization according to the presence or absence of data to drive the display, there is a period in which display is performed in an address state during one scanning period and a period in which a display is performed in a hold state. In addition, in the address state, the first part of the period is a period in which the same pulsed voltage as when no data is applied regardless of the presence or absence of data, and the period in which the pulse voltage is applied to the scanning electrode in the hold state. A method for driving a plasma display, characterized in that the frequency of the applied pulsed voltage is higher than at least the frequency of an address state. Note that the address state and hold state referred to here are defined as follows. That is, in synchronization with the pulsed voltage applied to the scan electrode during one scan period when one scan electrode is selected, and in addition, the data side electrode corresponding to the cell to be displayed has an opposite phase, and the cell that should not be displayed is synchronized with the pulse voltage applied to the scan electrode. The state during which a pulsed voltage of the same phase is applied to the data-side electrode corresponding to the display is called the address state, and the pulsed voltage that had been applied to the data-side electrode is stopped, and the charge created in the address state is called the address state. A state during a period in which the particles are driven only by pulsed voltages applied to the scanning electrodes is defined as a hold state.
JP62289903A 1987-11-16 1987-11-16 Driving method of plasma display Expired - Fee Related JP2576158B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62289903A JP2576158B2 (en) 1987-11-16 1987-11-16 Driving method of plasma display

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62289903A JP2576158B2 (en) 1987-11-16 1987-11-16 Driving method of plasma display

Publications (2)

Publication Number Publication Date
JPH01130192A true JPH01130192A (en) 1989-05-23
JP2576158B2 JP2576158B2 (en) 1997-01-29

Family

ID=17749264

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62289903A Expired - Fee Related JP2576158B2 (en) 1987-11-16 1987-11-16 Driving method of plasma display

Country Status (1)

Country Link
JP (1) JP2576158B2 (en)

Also Published As

Publication number Publication date
JP2576158B2 (en) 1997-01-29

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