JPH01126663U - - Google Patents
Info
- Publication number
- JPH01126663U JPH01126663U JP1770888U JP1770888U JPH01126663U JP H01126663 U JPH01126663 U JP H01126663U JP 1770888 U JP1770888 U JP 1770888U JP 1770888 U JP1770888 U JP 1770888U JP H01126663 U JPH01126663 U JP H01126663U
- Authority
- JP
- Japan
- Prior art keywords
- control signal
- circuit
- level
- period
- amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Television Receiver Circuits (AREA)
Description
第１図は本考案の画像調整回路の一実施例を示
す回路図、第２図は本考案の他の実施例の要部回
路図、第３図はドーミングを説明するための図、
第４図はブルーミングを説明するための図、第５
図は平均値型コントラスト回路の動作を説明する
ための図、第６図はピークリミツタ回路の動作を
説明するための図である。
２……コントラスト調整用増幅器、４……垂直
ブランキングパルス発生回路、５……端子、９…
…ピークレベル検出回路、１０……時定数回路。
FIG. 1 is a circuit diagram showing one embodiment of the image adjustment circuit of the present invention, FIG. 2 is a circuit diagram of a main part of another embodiment of the present invention, and FIG. 3 is a diagram for explaining doming.
Figure 4 is a diagram to explain blooming, Figure 5
This figure is a diagram for explaining the operation of the average value type contrast circuit, and FIG. 6 is a diagram for explaining the operation of the peak limiter circuit. 2... Contrast adjustment amplifier, 4... Vertical blanking pulse generation circuit, 5... Terminal, 9...
...Peak level detection circuit, 10...Time constant circuit.
Claims (1)
ルと基準レベルとを比較し、前記輝度信号のレベ
ルが前記基準レベルより超えると制御信号を出力
するピークレベル検出回路と、 前記ピークレベル検出回路からの制御信号を少
なくとも１垂直期間以上の所定期間保持するとと
もにコントラスト調整用増幅器に前記制御信号を
前記所定期間供給して前記増幅器の利得を減少せ
しめる制御信号保持回路と、 前記制御信号を垂直ブランキング期間は無効と
する制御信号無効回路とからなる画像調整回路。[Claims for Utility Model Registration] A peak level detection circuit that compares the level of a luminance signal applied to a luminance signal input terminal with a reference level, and outputs a control signal when the level of the luminance signal exceeds the reference level. , a control signal holding circuit that holds the control signal from the peak level detection circuit for a predetermined period of at least one vertical period or more, and supplies the control signal to a contrast adjustment amplifier for the predetermined period to reduce the gain of the amplifier; An image adjustment circuit comprising a control signal invalidating circuit that invalidates the control signal during a vertical blanking period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1770888U JPH0523022Y2 (en) | 1988-02-12 | 1988-02-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1770888U JPH0523022Y2 (en) | 1988-02-12 | 1988-02-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01126663U true JPH01126663U (en) | 1989-08-30 |
| JPH0523022Y2 JPH0523022Y2 (en) | 1993-06-14 |
Family
ID=31231731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1770888U Expired - Lifetime JPH0523022Y2 (en) | 1988-02-12 | 1988-02-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0523022Y2 (en) |
-
1988
- 1988-02-12 JP JP1770888U patent/JPH0523022Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0523022Y2 (en) | 1993-06-14 |
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