JPS6440927U

JPS6440927U -

Info

Publication number: JPS6440927U
Application number: JP13482187U
Authority: JP
Priority date: 1987-09-03
Filing date: 1987-09-03
Publication date: 1989-03-10

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例のブロツク図、第２
図は本考案の一実施例より出力されるデジタル信
号の分解能を説明するための図、第３図は従来の
利得自動調整装置の一例のブロツク図、第４図は
従来の利得自動調整装置より出力されるデジタル
信号の分解能を説明するための図である。１……Ａ／Ｄ変換器、１Ａ……アナログ入力端
子、１Ｂ……基準電圧入力端子、２……平均器、
３……比較器、４……乗算器。 Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a diagram for explaining the resolution of the digital signal output from an embodiment of the present invention, Figure 3 is a block diagram of an example of a conventional automatic gain adjustment device, and Figure 4 is a diagram of a conventional automatic gain adjustment device. FIG. 3 is a diagram for explaining the resolution of an output digital signal. 1...A/D converter, 1A...analog input terminal, 1B...reference voltage input terminal, 2...average device,
3... Comparator, 4... Multiplier.

Claims

[Claims for Utility Model Registration] (1) An A/D converter that converts an analog input into a digital output according to a reference voltage input to its reference voltage input terminal, and detects the average value of the digital output. An automatic gain adjustment device comprising: an averager; and reference voltage adjustment means for adjusting the reference voltage so that the average value matches a preset target value. (2) The reference voltage adjusting means includes: a comparator that compares the average value and the target value; and a first predetermined value a or a first Claim 1 of the above-mentioned utility model registration claim, comprising means for multiplying or dividing a value obtained by adding or subtracting a second predetermined value b or a multiple of the second predetermined value b to the predetermined value a. The automatic gain adjustment device described.