JPS5924226Y2 - Television receiver AGC circuit - Google Patents

Description

[Detailed explanation of the idea] The present invention relates to an AGC circuit for a television receiver.

Current television receivers use a so-called delay-type AGC circuit, which consists of, for example, a tuner 1, a video intermediate frequency amplification (VIP) circuit 2, and a video detection circuit 3, as shown in Figure 1. In a television receiver equipped with the above-mentioned video detection circuit 3, an AGC detection circuit 7 consisting of a transistor 4, a diode 5 for peak detection, and a capacitor 6, which uses the output of the video detection circuit 3 as a human power, outputs an A proportional to the antenna input level.
Deriving the GC detection output, controlling the gain of the VIP circuit 2 by obtaining the emitter output voltage generated in the resistor 9 of the transistor 8 for impedance conversion using the output as input, and using the emitter follower output of the transistor 8 as input. The gain of the tuner 1 is controlled by obtaining the collector output voltage of a signal delay transistor 11 whose base bias is varied by a variable resistor 10.

At this time, the resistors 12 and 13 are used to derive a constant voltage when the transistor 11 is off, thereby fixing the tuner 1 at the maximum gain.

That is, in this circuit, region A in FIG.
The emitter output voltage (IFAGC voltage) of VIP circuit 2
is lower than the gain control start voltage va of the tuner A, and the transistor 11 is also off, so that its collector voltage (tuner A
GC voltage) is fixed at the voltage VC at the midpoint of the connection between the resistors 12 and 13, and the tuner 1 and the VIP circuit 2 are operating at maximum gain.

In region B, the IFAGC voltage exceeds ■8, but the second transistor 11 is still off and only the gain of the VIP circuit 2 is being varied; in region C, the second transistor 11 is on. This is a state in which the gain of the tuner 1 is varied while the gain of the VIP circuit 2 is attenuated by a certain amount.

For the first time, in such an AGC circuit, transistor 4 is an emitter follower and has almost no amplification effect, but transistor 11 is a common base type and has an amplification effect.
If the C detection output contains video signal ripple, this ripple is amplified and fed back to tuner 1, resulting in so-called AGC oscillation, which sacrifices the stability of the AGC circuit. It was difficult to remove without.

However, the present invention proposes an AGC circuit that eliminates these drawbacks of the conventional example.

FIG. 2 shows an embodiment of the AGC circuit of the present invention, and the same components as in FIG. 1 are given the same reference numbers and their explanations will be omitted.

The feature of FIG. 2 is that a second transistor 15 is provided which operates from the active region to the saturation region in response to the emitter follower output of the first transistor 8 for impedance conversion supplied via the resistor 14. At this time, the collector bias of this transistor 15 is made variable by the variable resistor 16, and the gain of the tuner 1 is controlled by the emitter output voltage of this transistor generated in the resistor 17. The connection midpoint of voltage dividing resistors 18 and 19 (potential V.

), and the output voltage at the midpoint of the connection of this diode 20.21 is V.
The point is that the gain of the IP circuit 2 is controlled.

In the AGC circuit of the present invention having such a configuration, the area A in FIG. corresponds to
The emitter voltage of the first transistor 8 is V8 or higher, and
5 or less, one of the diodes 20 is off and the other 21
The case where is on corresponds to region B in FIG.

When the emitter voltage of the first transistor 8 becomes vb, the second transistor 15 is saturated and its IF
The AGC voltage is held constant, and this case corresponds to the boundary point between region B and region C, and in this state, V5 and V.

V in between. Since there is a potential difference of , the diode 20 is not turned on yet and the tuner 1 is still operating at maximum gain.

If the antenna input rises even slightly (within 1 dB) from this state, the emitter voltage of the first transistor 8 will rise rapidly, the diode 20 will immediately turn on, and the tuner 1 will then receive an AGC voltage according to the antenna input level. This is region C in FIG. 3 where appears.

Here, by adjusting the variable resistor 16, the second transistor 15 determines the antenna input level at which it enters the saturation region, so the tuner gain control starting point (the boundary point between regions B and C in FIG. 3) will also be at this point. can be moved left or right in the diagram depending on the

In the embodiment shown in FIG. 2, the AGC detection circuit 7 is of the peak detection type, but it goes without saying that it may be of the keyed detection type.

As described above, according to the present invention, the IFAGC voltage is taken out from the emitter follower transistor, and the tuner AGC voltage is delayed by limiting the IFAGC voltage and taken out via the switching diode. It is possible to realize an AGC circuit that is almost impossible,
It is suitable for implementation in a television receiver.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing a conventional AGC circuit, Fig. 2 is a circuit diagram showing an AGC circuit of the present invention, and Fig. 3 is a circuit diagram showing a conventional AGC circuit.
FIG. 3 is a characteristic diagram for explaining the circuit shown in the figure. 7: AGC detection circuit, 8: First transistor, 15
:2nd transistor, 20.21 Niswitching diode.

Claims (2)

[Scope of utility model registration request] (1) an emitter follower type first transistor that receives an AGC detection output proportional to the antenna input level; and an emitter follower type second transistor that changes from an active region to a saturation region according to the emitter follower output;
a switching diode that derives a constant voltage when the emitter output voltage of the first transistor is below a predetermined value and derives the emitter output voltage when it is above the predetermined value;
An AGC circuit for a television receiver, wherein the emitter output voltage of the second transistor is applied to a video intermediate frequency amplifier, and the output voltage of the switching diode is applied to a tuner. (2) The television receiver according to claim 1, wherein the collector bias voltage of the second transistor is variable, and the gain control start point of the tuner can be adjusted by changing the bias voltage. AG of
C circuit.